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anil.recoil.org
1opam-version: "2.0"
2synopsis:
3 "A lua client for interfacing hardcaml to verilator, UHDM, Verible and RTLIL front-ends"
4description:
5 "Verilator, Surelog and Verible do not generate synthesised Verilog code directly. This software bridges the gap and verifies the results using build-in minisat solver, z3 or external eqy script"
6maintainer: ["Jonathan Kimmitt"]
7authors: ["Jonathan Kimmitt"]
8license: "MIT"
9tags: ["Verilator" "Surelog" "UHDM" "Verible" "Yosys" "RTLIL"]
10# This option excludes win32 because Z3 apparently does not work
11# and flambda because it hangs (or takes a very long time) on my code for the present time.
12available: [ os != "win32" & arch != "riscv64" & arch != "riscv32" ]
13homepage: "https://github.com/jrrk2/hardcaml-lua"
14bug-reports: "https://github.com/jrrk2/hardcaml-lua/issues"
15depends: [
16 "dune" {>= "3.7"}
17 "xml-light"
18 "msat"
19 "menhir" {>= "20240715"}
20 "hardcaml"
21 "hardcaml_circuits" {>= "v0.17.0"}
22 "lua-ml"
23 "ppx_deriving_yojson"
24 "z3"
25 "odoc" {with-doc}
26]
27conflicts: [
28 "ocaml-option-flambda"
29]
30build: [
31 ["dune" "subst"] {dev}
32 [
33 "dune"
34 "build"
35 "-p"
36 name
37 "-j"
38 jobs
39 "@install"
40 "@runtest" {with-test}
41 "@doc" {with-doc}
42 ]
43]
44dev-repo: "git+https://github.com/jrrk2/hardcaml-lua.git"
45url {
46 src:
47 "https://github.com/jrrk2/hardcaml-lua/releases/download/0.0.1/hardcaml-lua-0.0.1.tbz"
48 checksum: [
49 "sha256=39d6b86d008d2d2408f178d0bd60ea54ea97a8e6f5d6491c9cb3314fe679cacf"
50 "sha512=b20915daa25687d2c8c75c3ed57d7c353d59a1873b6f544afe8ed4253f12105a3f586f2224191c054b330458296a1605510849201af8419b11b28d673dce057c"
51 ]
52}
53x-commit-hash: "20d824654422add31bb04d795111c7b981cc4fbf"