this repo has no description
anil.recoil.org
1opam-version: "2.0"
2maintainer: "Jane Street developers"
3authors: ["Jane Street Group, LLC"]
4homepage: "https://github.com/janestreet/hardcaml_of_verilog"
5bug-reports: "https://github.com/janestreet/hardcaml_of_verilog/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml_of_verilog.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_of_verilog/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "4.08.0"}
14 "base" {>= "v0.15" & < "v0.16"}
15 "core_unix" {>= "v0.15" & < "v0.16"}
16 "hardcaml" {>= "v0.15" & < "v0.16"}
17 "jsonaf" {>= "v0.15" & < "v0.16"}
18 "ppx_deriving_hardcaml" {>= "v0.15" & < "v0.16"}
19 "ppx_jane" {>= "v0.15" & < "v0.16"}
20 "ppx_jsonaf_conv" {>= "v0.15" & < "v0.16"}
21 "stdio" {>= "v0.15" & < "v0.16"}
22 "dune" {>= "2.0.0"}
23]
24synopsis: "Convert Verilog to a Hardcaml design"
25description: "
26The opensource synthesis tool yosys is used to convert a verilog design to a JSON based
27netlist representation. This library can load the JSON netlist and build a hardcaml
28circuit.
29
30Code can also be generated to wrap the conversion process using Hardcaml interfaces.
31"
32url {
33src: "https://ocaml.janestreet.com/ocaml-core/v0.15/files/hardcaml_of_verilog-v0.15.0.tar.gz"
34checksum: "sha256=2548df37bf5dae8a61f6042e2bb1120272697b1b331707f9989d267890c3ee0d"
35}