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anil.recoil.org
1opam-version: "2.0"
2maintainer: "Jane Street developers"
3authors: ["Jane Street Group, LLC"]
4homepage: "https://github.com/janestreet/hardcaml"
5bug-reports: "https://github.com/janestreet/hardcaml/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "4.07.0"}
14 "base" {>= "v0.12" & < "v0.13"}
15 "ppx_jane" {>= "v0.12" & < "v0.13"}
16 "stdio" {>= "v0.12" & < "v0.13"}
17 "topological_sort" {>= "v0.12" & < "v0.13"}
18 "dune" {>= "1.5.1"}
19 "zarith" {>= "1.5"}
20]
21synopsis: "RTL Hardware Design in OCaml"
22description: "
23Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
24Generic hardware designs are easily expressed using features such as higher
25order functions, lists, maps etc. A built in simulator allows designs to
26be simulated within Hardcaml. Designs are converted to either Verilog or
27VHDL to interact with standard back end tooling.
28"
29url {
30 src:
31 "https://ocaml.janestreet.com/ocaml-core/v0.12/files/hardcaml-v0.12.0.tar.gz"
32 checksum: [
33 "sha256=1bef834dd9105c26530600cd6a211727004af0741fe39376682fb833fda8b918"
34 "md5=bddd766d20ca9d90d3d4d0d521e0d2b2"
35 ]
36}