this repo has no description
anil.recoil.org
1opam-version: "2.0"
2maintainer: "Jane Street developers"
3authors: ["Jane Street Group, LLC"]
4homepage: "https://github.com/janestreet/hardcaml_of_verilog"
5bug-reports: "https://github.com/janestreet/hardcaml_of_verilog/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml_of_verilog.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_of_verilog/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "5.1.0"}
14 "base" {>= "v0.17" & < "v0.18"}
15 "core" {>= "v0.17" & < "v0.18"}
16 "core_unix" {>= "v0.17" & < "v0.18"}
17 "hardcaml" {>= "v0.17" & < "v0.18"}
18 "hardcaml_verify" {>= "v0.17" & < "v0.18"}
19 "jsonaf" {>= "v0.17" & < "v0.18"}
20 "ppx_hardcaml" {>= "v0.17" & < "v0.18"}
21 "ppx_jane" {>= "v0.17" & < "v0.18"}
22 "ppx_jsonaf_conv" {>= "v0.17" & < "v0.18"}
23 "stdio" {>= "v0.17" & < "v0.18"}
24 "dune" {>= "3.11.0"}
25]
26available: arch != "arm32" & arch != "x86_32"
27synopsis: "Convert Verilog to a Hardcaml design"
28description: "
29The opensource synthesis tool yosys is used to convert a verilog design to a JSON based
30netlist representation. This library can load the JSON netlist and build a hardcaml
31circuit.
32
33Code can also be generated to wrap the conversion process using Hardcaml interfaces.
34"
35url {
36src: "https://github.com/janestreet/hardcaml_of_verilog/archive/refs/tags/v0.17.0.tar.gz"
37checksum: "sha256=8603da93ce48dc3e550043310ab3b5c0da3bc19f04391ade7bcc8c46dc3e612d"
38}