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anil.recoil.org
1opam-version: "2.0"
2maintainer: "Jane Street developers"
3authors: ["Jane Street Group, LLC"]
4homepage: "https://github.com/janestreet/hardcaml"
5bug-reports: "https://github.com/janestreet/hardcaml/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "4.07.0"}
14 "base" {>= "v0.14" & < "v0.15"}
15 "ppx_jane" {>= "v0.14" & < "v0.15"}
16 "ppx_sexp_conv" {>= "v0.14" & < "v0.15"}
17 "stdio" {>= "v0.14" & < "v0.15"}
18 "topological_sort" {>= "v0.14" & < "v0.15"}
19 "dune" {>= "2.0.0"}
20 "ppxlib" {>= "0.11.0" & < "0.18.0"}
21 "zarith" {>= "1.5"}
22]
23synopsis: "RTL Hardware Design in OCaml"
24description: "
25Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
26Generic hardware designs are easily expressed using features such as higher
27order functions, lists, maps etc. A built in simulator allows designs to
28be simulated within Hardcaml. Designs are converted to either Verilog or
29VHDL to interact with standard back end tooling.
30"
31url {
32 src:
33 "https://ocaml.janestreet.com/ocaml-core/v0.14/files/hardcaml-v0.14.0.tar.gz"
34 checksum: [
35 "sha256=465e94af73a83517bff9880803d183fa5f1e6a41702cf27d44329c0c64ff6e1d"
36 "md5=238d2dc37f029802217f883f64f7445d"
37 ]
38}