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anil.recoil.org
1opam-version: "2.0"
2maintainer: "opensource@janestreet.com"
3authors: ["Jane Street Group, LLC <opensource@janestreet.com>"]
4homepage: "https://github.com/janestreet/hardcaml"
5bug-reports: "https://github.com/janestreet/hardcaml/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "4.07.0"}
14 "base" {>= "v0.14" & < "v0.15"}
15 "ppx_jane" {>= "v0.14" & < "v0.15"}
16 "ppx_sexp_conv" {>= "v0.14" & < "v0.15"}
17 "stdio" {>= "v0.14" & < "v0.15"}
18 "topological_sort" {>= "v0.14" & < "v0.15"}
19 "dune" {>= "2.0.0"}
20 "ppxlib" {>= "0.18.0"}
21 "zarith" {>= "1.5"}
22]
23available: arch != "arm32" & arch != "x86_32"
24synopsis: "RTL Hardware Design in OCaml"
25description: "
26Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
27Generic hardware designs are easily expressed using features such as higher
28order functions, lists, maps etc. A built in simulator allows designs to
29be simulated within Hardcaml. Designs are converted to either Verilog or
30VHDL to interact with standard back end tooling.
31"
32url {
33 src: "https://github.com/janestreet/hardcaml/archive/v0.14.2.tar.gz"
34 checksum: [
35 "sha256=bc3de7234e8ceb3192f5b19f762619afcf549497df817eace6de8ae0ff91bc8d"
36 "md5=392c84bfcf1e9931f40bbbbb995f7b0a"
37 ]
38}