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anil.recoil.org
1opam-version: "2.0"
2maintainer: "Jane Street developers"
3authors: ["Jane Street Group, LLC"]
4homepage: "https://github.com/janestreet/hardcaml"
5bug-reports: "https://github.com/janestreet/hardcaml/issues"
6dev-repo: "git+https://github.com/janestreet/hardcaml.git"
7doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
8license: "MIT"
9build: [
10 ["dune" "build" "-p" name "-j" jobs]
11]
12depends: [
13 "ocaml" {>= "4.14.0"}
14 "base" {>= "v0.16" & < "v0.17"}
15 "bin_prot" {>= "v0.16" & < "v0.17"}
16 "core_kernel" {>= "v0.16" & < "v0.17"}
17 "ppx_jane" {>= "v0.16" & < "v0.17"}
18 "ppx_sexp_conv" {>= "v0.16" & < "v0.17"}
19 "stdio" {>= "v0.16" & < "v0.17"}
20 "topological_sort" {>= "v0.16" & < "v0.17"}
21 "dune" {>= "2.0.0"}
22 "ppxlib" {>= "0.28.0"}
23 "zarith" {>= "1.11"}
24]
25synopsis: "RTL Hardware Design in OCaml"
26description: "
27Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
28Generic hardware designs are easily expressed using features such as higher
29order functions, lists, maps etc. A built in simulator allows designs to
30be simulated within Hardcaml. Designs are converted to either Verilog or
31VHDL to interact with standard back end tooling.
32"
33url {
34src: "https://ocaml.janestreet.com/ocaml-core/v0.16/files/hardcaml-v0.16.0.tar.gz"
35checksum: "sha256=1cc136550365918c5e72db328acf7bbf109f680bdacb60edb80972dee042a58d"
36}