opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml_of_verilog"
bug-reports: "https://github.com/janestreet/hardcaml_of_verilog/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml_of_verilog.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_of_verilog/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"                 {>= "4.14.0"}
  "base"                  {>= "v0.16" & < "v0.17"}
  "core"                  {>= "v0.16" & < "v0.17"}
  "core_unix"             {>= "v0.16" & < "v0.17"}
  "hardcaml"              {>= "v0.16" & < "v0.17"}
  "hardcaml_verify"       {>= "v0.16" & < "v0.17"}
  "jsonaf"                {>= "v0.16" & < "v0.17"}
  "ppx_deriving_hardcaml" {>= "v0.16" & < "v0.17"}
  "ppx_jane"              {>= "v0.16" & < "v0.17"}
  "ppx_jsonaf_conv"       {>= "v0.16" & < "v0.17"}
  "stdio"                 {>= "v0.16" & < "v0.17"}
  "dune"                  {>= "2.0.0"}
]
synopsis: "Convert Verilog to a Hardcaml design"
description: "
The opensource synthesis tool yosys is used to convert a verilog design to a JSON based
netlist representation. This library can load the JSON netlist and build a hardcaml
circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.
"
url {
src: "https://ocaml.janestreet.com/ocaml-core/v0.16/files/hardcaml_of_verilog-v0.16.0.tar.gz"
checksum: "sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4"
}