opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml"
bug-reports: "https://github.com/janestreet/hardcaml/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"            {>= "4.14.0"}
  "base"             {>= "v0.16" & < "v0.17"}
  "bin_prot"         {>= "v0.16" & < "v0.17"}
  "core_kernel"      {>= "v0.16" & < "v0.17"}
  "ppx_jane"         {>= "v0.16" & < "v0.17"}
  "ppx_sexp_conv"    {>= "v0.16" & < "v0.17"}
  "stdio"            {>= "v0.16" & < "v0.17"}
  "topological_sort" {>= "v0.16" & < "v0.17"}
  "dune"             {>= "2.0.0"}
  "ppxlib"           {>= "0.28.0"}
  "zarith"           {>= "1.11"}
]
synopsis: "RTL Hardware Design in OCaml"
description: "
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
Generic hardware designs are easily expressed using features such as higher
order functions, lists, maps etc.  A built in simulator allows designs to
be simulated within Hardcaml.  Designs are converted to either Verilog or
VHDL to interact with standard back end tooling.
"
url {
src: "https://ocaml.janestreet.com/ocaml-core/v0.16/files/hardcaml-v0.16.0.tar.gz"
checksum: "sha256=1cc136550365918c5e72db328acf7bbf109f680bdacb60edb80972dee042a58d"
}