opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml"
bug-reports: "https://github.com/janestreet/hardcaml/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"            {>= "4.07.0"}
  "base"             {>= "v0.13" & < "v0.14"}
  "ppx_jane"         {>= "v0.13" & < "v0.14"}
  "stdio"            {>= "v0.13" & < "v0.14"}
  "topological_sort" {>= "v0.13" & < "v0.14"}
  "dune"             {>= "1.5.1"}
  "zarith"           {>= "1.5"}
]
synopsis: "RTL Hardware Design in OCaml"
description: "
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
Generic hardware designs are easily expressed using features such as higher
order functions, lists, maps etc.  A built in simulator allows designs to
be simulated within Hardcaml.  Designs are converted to either Verilog or
VHDL to interact with standard back end tooling.
"
url {
  src:
    "https://ocaml.janestreet.com/ocaml-core/v0.13/files/hardcaml-v0.13.0.tar.gz"
  checksum: [
    "sha256=9f7bb189c6de2bfb8d6bb060360148578e48e1d014c2c82bba48e18972bbbf5a"
    "md5=692be272e1fee9515b3b0fd16f9a1a6d"
  ]
}