opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml"
bug-reports: "https://github.com/janestreet/hardcaml/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"            {>= "4.07.0"}
  "base"             {>= "v0.14" & < "v0.15"}
  "ppx_jane"         {>= "v0.14" & < "v0.15"}
  "ppx_sexp_conv"    {>= "v0.14" & < "v0.15"}
  "stdio"            {>= "v0.14" & < "v0.15"}
  "topological_sort" {>= "v0.14" & < "v0.15"}
  "dune"             {>= "2.0.0"}
  "ppxlib"           {>= "0.11.0" & < "0.18.0"}
  "zarith"           {>= "1.5"}
]
synopsis: "RTL Hardware Design in OCaml"
description: "
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml.
Generic hardware designs are easily expressed using features such as higher
order functions, lists, maps etc.  A built in simulator allows designs to
be simulated within Hardcaml.  Designs are converted to either Verilog or
VHDL to interact with standard back end tooling.
"
url {
  src:
    "https://ocaml.janestreet.com/ocaml-core/v0.14/files/hardcaml-v0.14.0.tar.gz"
  checksum: [
    "sha256=465e94af73a83517bff9880803d183fa5f1e6a41702cf27d44329c0c64ff6e1d"
    "md5=238d2dc37f029802217f883f64f7445d"
  ]
}