opam-version: "2.0"
maintainer: "Jane Street developers"
authors: ["Jane Street Group, LLC"]
homepage: "https://github.com/janestreet/hardcaml_xilinx"
bug-reports: "https://github.com/janestreet/hardcaml_xilinx/issues"
dev-repo: "git+https://github.com/janestreet/hardcaml_xilinx.git"
doc: "https://ocaml.janestreet.com/ocaml-core/latest/doc/hardcaml_xilinx/index.html"
license: "MIT"
build: [
  ["dune" "build" "-p" name "-j" jobs]
]
depends: [
  "ocaml"        {>= "5.1.0"}
  "base"         {>= "v0.17" & < "v0.18"}
  "hardcaml"     {>= "v0.17" & < "v0.18"}
  "n_ary"        {>= "v0.17" & < "v0.18"}
  "ppx_hardcaml" {>= "v0.17" & < "v0.18"}
  "ppx_jane"     {>= "v0.17" & < "v0.18"}
  "dune"         {>= "3.11.0"}
]
available: arch != "arm32" & arch != "x86_32"
synopsis: "Hardcaml wrappers for Xilinx memory primitives"
description: "
The Hardcaml_xilinx library provides wrappers for Xilinx specific RAM and FIFO primitive
blocks. In many cases a simulation model is provided.

The `Synthesis` module implements various arithmetic and logical RTL components with
Xilinx LUT primitives.
"
url {
src: "https://github.com/janestreet/hardcaml_xilinx/archive/refs/tags/v0.17.0.tar.gz"
checksum: "sha256=01df85cf275569447f3c8f1ad03bbae5f8751afbb886833be875aedda9ae3288"
}