···
0x00 => self.brk(pins), // BRK
113
-
0x01 => if (self.zpXInd(pins)) self.ora(pins, v), // ORA (zp,X)
114
-
0x05 => if (self.zp(pins)) self.ora(pins, v), // ORA zp
115
-
0x06 => if (self.zp(pins)) self.asl(pins, .mem), // ASL zp
116
-
0x09 => if (self.imm(pins)) self.ora(pins, v), // ORA #
117
-
0x0a => if (self.imm(pins)) self.asl(pins, .acc), // ASL A
118
-
0x0d => if (self.abs(pins)) self.ora(pins, v), // ORA abs
119
-
0x0e => if (self.abs(pins)) self.asl(pins, .mem), // ASL abs
121
-
0x10 => if (self.imm(pins)) self.branch(pins, !self.status.negative), // BPL
122
-
0x11 => if (self.zpIndY(pins)) self.ora(pins, v), // ORA (zp),Y
123
-
0x15 => if (self.zpOff(pins, self.x)) self.ora(pins, v), // ORA zp,X
124
-
0x16 => if (self.zpOff(pins, self.x)) self.asl(pins, .mem), // ASL zp,X
112
+
0x01 => if (self.zpXInd(pins)) |_| self.ora(pins, v), // ORA (zp,X)
113
+
0x05 => if (self.zp(pins)) |_| self.ora(pins, v), // ORA zp
114
+
0x06 => if (self.zp(pins)) |_| self.asl(pins, .mem), // ASL zp
115
+
0x09 => if (self.imm(pins)) |_| self.ora(pins, v), // ORA #
116
+
0x0a => if (self.imm(pins)) |_| self.asl(pins, .acc), // ASL A
117
+
0x0d => if (self.abs(pins)) |_| self.ora(pins, v), // ORA abs
118
+
0x0e => if (self.abs(pins)) |_| self.asl(pins, .mem), // ASL abs
120
+
0x10 => if (self.imm(pins)) |_| self.branch(pins, !self.status.negative), // BPL
121
+
0x11 => if (self.zpIndY(pins)) |_| self.ora(pins, v), // ORA (zp),Y
122
+
0x15 => if (self.zpOff(pins, self.x)) |_| self.ora(pins, v), // ORA zp,X
123
+
0x16 => if (self.zpOff(pins, self.x)) |_| self.asl(pins, .mem), // ASL zp,X
0x18 => self.set(pins, .carry, false), // CLC
126
-
0x19 => if (self.absOff(pins, self.y)) self.ora(pins, v), // ORA abs,Y
127
-
0x1d => if (self.absOff(pins, self.x)) self.ora(pins, v), // ORA abs,X
128
-
0x1e => if (self.absOff(pins, self.x)) self.asl(pins, .mem), // ASL abs,X
130
-
0x21 => if (self.zpXInd(pins)) self._and(pins, v), // AND (zp,X)
131
-
0x25 => if (self.zp(pins)) self._and(pins, v), // AND zp
132
-
0x26 => if (self.zp(pins)) self.rol(pins, .mem), // ROL zp
133
-
0x29 => if (self.imm(pins)) self._and(pins, v), // AND #
134
-
0x2a => if (self.imm(pins)) self.rol(pins, .acc), // ROL A
135
-
0x2d => if (self.abs(pins)) self._and(pins, v), // AND abs
136
-
0x2e => if (self.abs(pins)) self.rol(pins, .mem), // ROL abs
138
-
0x30 => if (self.imm(pins)) self.branch(pins, self.status.negative), // BMI
139
-
0x31 => if (self.zpIndY(pins)) self._and(pins, v), // AND (zp),Y
140
-
0x35 => if (self.zpOff(pins, self.x)) self._and(pins, v), // AND zp,X
141
-
0x36 => if (self.zpOff(pins, self.x)) self.rol(pins, .mem), // ROL zp,X
125
+
0x19 => if (self.absOff(pins, self.y)) |_| self.ora(pins, v), // ORA abs,Y
126
+
0x1d => if (self.absOff(pins, self.x)) |_| self.ora(pins, v), // ORA abs,X
127
+
0x1e => if (self.absOff(pins, self.x)) |_| self.asl(pins, .mem), // ASL abs,X
129
+
0x21 => if (self.zpXInd(pins)) |_| self._and(pins, v), // AND (zp,X)
130
+
0x24 => if (self.zp(pins)) |_| self.bit(pins), // BIT zp
131
+
0x25 => if (self.zp(pins)) |_| self._and(pins, v), // AND zp
132
+
0x26 => if (self.zp(pins)) |_| self.rol(pins, .mem), // ROL zp
133
+
0x29 => if (self.imm(pins)) |_| self._and(pins, v), // AND #
134
+
0x2a => if (self.imm(pins)) |_| self.rol(pins, .acc), // ROL A
135
+
0x2c => if (self.abs(pins)) |_| self.bit(pins), // BIT abs
136
+
0x2d => if (self.abs(pins)) |_| self._and(pins, v), // AND abs
137
+
0x2e => if (self.abs(pins)) |_| self.rol(pins, .mem), // ROL abs
139
+
0x30 => if (self.imm(pins)) |_| self.branch(pins, self.status.negative), // BMI
140
+
0x31 => if (self.zpIndY(pins)) |_| self._and(pins, v), // AND (zp),Y
141
+
0x35 => if (self.zpOff(pins, self.x)) |_| self._and(pins, v), // AND zp,X
142
+
0x36 => if (self.zpOff(pins, self.x)) |_| self.rol(pins, .mem), // ROL zp,X
0x38 => self.set(pins, .carry, true), // SEC
143
-
0x39 => if (self.absOff(pins, self.y)) self._and(pins, v), // AND abs,Y
144
-
0x3d => if (self.absOff(pins, self.x)) self._and(pins, v), // AND abs,X
145
-
0x3e => if (self.absOff(pins, self.x)) self.rol(pins, .mem), // ROL abs,X
144
+
0x39 => if (self.absOff(pins, self.y)) |_| self._and(pins, v), // AND abs,Y
145
+
0x3d => if (self.absOff(pins, self.x)) |_| self._and(pins, v), // AND abs,X
146
+
0x3e => if (self.absOff(pins, self.x)) |_| self.rol(pins, .mem), // ROL abs,X
0x40 => self.rti(pins), // RTI
148
-
0x41 => if (self.zpXInd(pins)) self.eor(pins, v), // EOR (zp,X)
149
-
0x45 => if (self.zp(pins)) self.eor(pins, v), // EOR zp
150
-
0x46 => if (self.zp(pins)) self.lsr(pins, .mem), // LSR zp
151
-
0x49 => if (self.imm(pins)) self.eor(pins, v), // EOR #
152
-
0x4a => if (self.imm(pins)) self.lsr(pins, .acc), // LSR A
153
-
0x4d => if (self.abs(pins)) self.eor(pins, v), // EOR abs
154
-
0x4e => if (self.abs(pins)) self.lsr(pins, .mem), // LSR abs
156
-
0x50 => if (self.imm(pins)) self.branch(pins, !self.status.overflow), // BVC
157
-
0x51 => if (self.zpIndY(pins)) self.eor(pins, v), // EOR (zp),Y
158
-
0x55 => if (self.zpOff(pins, self.x)) self.eor(pins, v), // EOR zp,X
159
-
0x56 => if (self.zpOff(pins, self.x)) self.lsr(pins, .mem), // LSR zp,X
149
+
0x41 => if (self.zpXInd(pins)) |_| self.eor(pins, v), // EOR (zp,X)
150
+
0x45 => if (self.zp(pins)) |_| self.eor(pins, v), // EOR zp
151
+
0x46 => if (self.zp(pins)) |_| self.lsr(pins, .mem), // LSR zp
152
+
0x49 => if (self.imm(pins)) |_| self.eor(pins, v), // EOR #
153
+
0x4a => if (self.imm(pins)) |_| self.lsr(pins, .acc), // LSR A
154
+
0x4d => if (self.abs(pins)) |_| self.eor(pins, v), // EOR abs
155
+
0x4e => if (self.abs(pins)) |_| self.lsr(pins, .mem), // LSR abs
157
+
0x50 => if (self.imm(pins)) |_| self.branch(pins, !self.status.overflow), // BVC
158
+
0x51 => if (self.zpIndY(pins)) |_| self.eor(pins, v), // EOR (zp),Y
159
+
0x55 => if (self.zpOff(pins, self.x)) |_| self.eor(pins, v), // EOR zp,X
160
+
0x56 => if (self.zpOff(pins, self.x)) |_| self.lsr(pins, .mem), // LSR zp,X
0x58 => self.set(pins, .irq_disabled, false), // CLI
161
-
0x59 => if (self.absOff(pins, self.y)) self.eor(pins, v), // EOR abs,Y
162
-
0x5d => if (self.absOff(pins, self.x)) self.eor(pins, v), // EOR abs,X
163
-
0x5e => if (self.absOff(pins, self.x)) self.lsr(pins, .mem), // LSR abs,X
165
-
// 0x61 => if (self.zpXInd(pins)) self.adc(pins, v), // ADC (zp,X)
166
-
// 0x65 => if (self.zp(pins)) self.adc(pins, v), // ADC zp
167
-
0x66 => if (self.zp(pins)) self.ror(pins, .mem), // ROR zp
168
-
// 0x69 => if (self.imm(pins)) self.adc(pins, v), // ADC #
169
-
0x6a => if (self.imm(pins)) self.ror(pins, .acc), // ROR A
170
-
// 0x6d => if (self.abs(pins)) self.adc(pins, v), // ADC abs
171
-
0x6e => if (self.abs(pins)) self.ror(pins, .mem), // ROR abs
173
-
0x70 => if (self.imm(pins)) self.branch(pins, self.status.overflow), // BVS
174
-
// 0x71 => if (self.zpIndY(pins)) self.adc(pins, v), // ADC (zp),Y
175
-
// 0x75 => if (self.zpOff(pins, self.x)) self.adc(pins, v), // ADC zp,X
176
-
0x76 => if (self.zpOff(pins, self.x)) self.ror(pins, .mem), // ROR zp,X
162
+
0x59 => if (self.absOff(pins, self.y)) |_| self.eor(pins, v), // EOR abs,Y
163
+
0x5d => if (self.absOff(pins, self.x)) |_| self.eor(pins, v), // EOR abs,X
164
+
0x5e => if (self.absOff(pins, self.x)) |_| self.lsr(pins, .mem), // LSR abs,X
166
+
0x61 => if (self.zpXInd(pins)) |_| self.adc(pins, v), // ADC (zp,X)
167
+
0x65 => if (self.zp(pins)) |_| self.adc(pins, v), // ADC zp
168
+
0x66 => if (self.zp(pins)) |_| self.ror(pins, .mem), // ROR zp
169
+
0x69 => if (self.imm(pins)) |_| self.adc(pins, v), // ADC #
170
+
0x6a => if (self.imm(pins)) |_| self.ror(pins, .acc), // ROR A
171
+
0x6d => if (self.abs(pins)) |_| self.adc(pins, v), // ADC abs
172
+
0x6e => if (self.abs(pins)) |_| self.ror(pins, .mem), // ROR abs
174
+
0x70 => if (self.imm(pins)) |_| self.branch(pins, self.status.overflow), // BVS
175
+
0x71 => if (self.zpIndY(pins)) |_| self.adc(pins, v), // ADC (zp),Y
176
+
0x75 => if (self.zpOff(pins, self.x)) |_| self.adc(pins, v), // ADC zp,X
177
+
0x76 => if (self.zpOff(pins, self.x)) |_| self.ror(pins, .mem), // ROR zp,X
0x78 => self.set(pins, .irq_disabled, true), // SEI
178
-
// 0x79 => if (self.absOff(pins, self.y)) self.adc(pins, v), // ADC abs,Y
179
-
// 0x7d => if (self.absOff(pins, self.x)) self.adc(pins, v), // ADC abs,X
180
-
0x7e => if (self.absOff(pins, self.x)) self.ror(pins, .mem), // ROR abs,X
182
-
0x81 => if (self.zpXInd(pins)) self.st(pins, self.y), // STA (zp,X)
183
-
0x84 => if (self.zp(pins)) self.st(pins, self.y), // STY zp
184
-
0x85 => if (self.zp(pins)) self.st(pins, self.a), // STA zp
185
-
0x86 => if (self.zp(pins)) self.st(pins, self.x), // STX zp
186
-
0x88 => if (self.imm(pins)) self.dec(pins, &self.y), // DEY
187
-
0x8a => if (self.imm(pins)) self.ld(pins, &self.a, self.x), // TXA
188
-
0x8c => if (self.abs(pins)) self.st(pins, self.y), // STY abs
189
-
0x8d => if (self.abs(pins)) self.st(pins, self.a), // STA abs
190
-
0x8e => if (self.abs(pins)) self.st(pins, self.x), // STX abs
192
-
0x90 => if (self.imm(pins)) self.branch(pins, !self.status.carry), // BCC
193
-
0x91 => if (self.zpIndY(pins)) self.ld(pins, &self.a, v), // STA (zp),Y
194
-
0x94 => if (self.zpOff(pins, self.x)) self.st(pins, self.y), // STY zp,X
195
-
0x95 => if (self.zpOff(pins, self.x)) self.st(pins, self.a), // STA zp,X
196
-
0x96 => if (self.zpOff(pins, self.y)) self.st(pins, self.x), // STX zp,Y
197
-
0x99 => if (self.absOff(pins, self.y)) self.st(pins, self.a), // STA abs,Y
198
-
0x9a => if (self.imm(pins)) self.ld(pins, &self.sp, self.x), // TXS
199
-
0x9c => if (self.absOff(pins, self.x)) self.st(pins, self.y), // STY abs,X
200
-
0x9d => if (self.absOff(pins, self.x)) self.st(pins, self.a), // STA abs,X
201
-
0x9e => if (self.absOff(pins, self.y)) self.st(pins, self.x), // STX abs,Y
203
-
0xa0 => if (self.imm(pins)) self.ld(pins, &self.y, v), // LDY #
204
-
0xa1 => if (self.zpXInd(pins)) self.ld(pins, &self.y, v), // LDA (zp,X)
205
-
0xa2 => if (self.imm(pins)) self.ld(pins, &self.x, v), // LDX #
206
-
0xa4 => if (self.zp(pins)) self.ld(pins, &self.y, v), // LDY zp
207
-
0xa5 => if (self.zp(pins)) self.ld(pins, &self.a, v), // LDA zp
208
-
0xa6 => if (self.zp(pins)) self.ld(pins, &self.x, v), // LDX zp
209
-
0xa8 => if (self.imm(pins)) self.ld(pins, &self.y, self.a), // TAY
210
-
0xa9 => if (self.imm(pins)) self.ld(pins, &self.a, v), // LDA #
211
-
0xaa => if (self.imm(pins)) self.ld(pins, &self.x, self.a), // TAX
212
-
0xac => if (self.abs(pins)) self.ld(pins, &self.y, v), // LDY abs
213
-
0xad => if (self.abs(pins)) self.ld(pins, &self.a, v), // LDA abs
214
-
0xae => if (self.abs(pins)) self.ld(pins, &self.x, v), // LDX abs
216
-
0xb0 => if (self.imm(pins)) self.branch(pins, self.status.carry), // BCS
217
-
0xb1 => if (self.zpIndY(pins)) self.ld(pins, &self.a, v), // LDA (zp),Y
218
-
0xb4 => if (self.zpOff(pins, self.x)) self.ld(pins, &self.y, v), // LDY zp,X
219
-
0xb5 => if (self.zpOff(pins, self.x)) self.ld(pins, &self.a, v), // LDA zp,X
220
-
0xb6 => if (self.zpOff(pins, self.y)) self.ld(pins, &self.x, v), // LDX zp,Y
179
+
0x79 => if (self.absOff(pins, self.y)) |_| self.adc(pins, v), // ADC abs,Y
180
+
0x7d => if (self.absOff(pins, self.x)) |_| self.adc(pins, v), // ADC abs,X
181
+
0x7e => if (self.absOff(pins, self.x)) |_| self.ror(pins, .mem), // ROR abs,X
183
+
0x81 => if (self.zpXInd(pins)) |_| self.st(pins, self.y), // STA (zp,X)
184
+
0x84 => if (self.zp(pins)) |_| self.st(pins, self.y), // STY zp
185
+
0x85 => if (self.zp(pins)) |_| self.st(pins, self.a), // STA zp
186
+
0x86 => if (self.zp(pins)) |_| self.st(pins, self.x), // STX zp
187
+
0x88 => if (self.imm(pins)) |_| self.dexy(pins, &self.y), // DEY
188
+
0x8a => if (self.imm(pins)) |_| self.ld(pins, &self.a, self.x), // TXA
189
+
0x8c => if (self.abs(pins)) |_| self.st(pins, self.y), // STY abs
190
+
0x8d => if (self.abs(pins)) |_| self.st(pins, self.a), // STA abs
191
+
0x8e => if (self.abs(pins)) |_| self.st(pins, self.x), // STX abs
193
+
0x90 => if (self.imm(pins)) |_| self.branch(pins, !self.status.carry), // BCC
194
+
0x91 => if (self.zpIndY(pins)) |_| self.ld(pins, &self.a, v), // STA (zp),Y
195
+
0x94 => if (self.zpOff(pins, self.x)) |_| self.st(pins, self.y), // STY zp,X
196
+
0x95 => if (self.zpOff(pins, self.x)) |_| self.st(pins, self.a), // STA zp,X
197
+
0x96 => if (self.zpOff(pins, self.y)) |_| self.st(pins, self.x), // STX zp,Y
198
+
0x99 => if (self.absOff(pins, self.y)) |_| self.st(pins, self.a), // STA abs,Y
199
+
0x9a => if (self.imm(pins)) |_| self.ld(pins, &self.sp, self.x), // TXS
200
+
0x9c => if (self.absOff(pins, self.x)) |_| self.st(pins, self.y), // STY abs,X
201
+
0x9d => if (self.absOff(pins, self.x)) |_| self.st(pins, self.a), // STA abs,X
202
+
0x9e => if (self.absOff(pins, self.y)) |_| self.st(pins, self.x), // STX abs,Y
204
+
0xa0 => if (self.imm(pins)) |_| self.ld(pins, &self.y, v), // LDY #
205
+
0xa1 => if (self.zpXInd(pins)) |_| self.ld(pins, &self.y, v), // LDA (zp,X)
206
+
0xa2 => if (self.imm(pins)) |_| self.ld(pins, &self.x, v), // LDX #
207
+
0xa4 => if (self.zp(pins)) |_| self.ld(pins, &self.y, v), // LDY zp
208
+
0xa5 => if (self.zp(pins)) |_| self.ld(pins, &self.a, v), // LDA zp
209
+
0xa6 => if (self.zp(pins)) |_| self.ld(pins, &self.x, v), // LDX zp
210
+
0xa8 => if (self.imm(pins)) |_| self.ld(pins, &self.y, self.a), // TAY
211
+
0xa9 => if (self.imm(pins)) |_| self.ld(pins, &self.a, v), // LDA #
212
+
0xaa => if (self.imm(pins)) |_| self.ld(pins, &self.x, self.a), // TAX
213
+
0xac => if (self.abs(pins)) |_| self.ld(pins, &self.y, v), // LDY abs
214
+
0xad => if (self.abs(pins)) |_| self.ld(pins, &self.a, v), // LDA abs
215
+
0xae => if (self.abs(pins)) |_| self.ld(pins, &self.x, v), // LDX abs
217
+
0xb0 => if (self.imm(pins)) |_| self.branch(pins, self.status.carry), // BCS
218
+
0xb1 => if (self.zpIndY(pins)) |_| self.ld(pins, &self.a, v), // LDA (zp),Y
219
+
0xb4 => if (self.zpOff(pins, self.x)) |_| self.ld(pins, &self.y, v), // LDY zp,X
220
+
0xb5 => if (self.zpOff(pins, self.x)) |_| self.ld(pins, &self.a, v), // LDA zp,X
221
+
0xb6 => if (self.zpOff(pins, self.y)) |_| self.ld(pins, &self.x, v), // LDX zp,Y
0xb8 => self.set(pins, .overflow, true), // SEV
222
-
0xb9 => if (self.absOff(pins, self.y)) self.ld(pins, &self.a, v), // LDA abs,Y
223
-
0xba => if (self.imm(pins)) self.ld(pins, &self.x, self.sp), // TSX
224
-
0xbc => if (self.absOff(pins, self.x)) self.ld(pins, &self.y, v), // LDY abs,X
225
-
0xbd => if (self.absOff(pins, self.x)) self.ld(pins, &self.a, v), // LDA abs,X
226
-
0xbe => if (self.absOff(pins, self.y)) self.ld(pins, &self.x, v), // LDX abs,Y
228
-
0xd0 => if (self.imm(pins)) self.branch(pins, !self.status.zero), // BNE
223
+
0xb9 => if (self.absOff(pins, self.y)) |_| self.ld(pins, &self.a, v), // LDA abs,Y
224
+
0xba => if (self.imm(pins)) |_| self.ld(pins, &self.x, self.sp), // TSX
225
+
0xbc => if (self.absOff(pins, self.x)) |_| self.ld(pins, &self.y, v), // LDY abs,X
226
+
0xbd => if (self.absOff(pins, self.x)) |_| self.ld(pins, &self.a, v), // LDA abs,X
227
+
0xbe => if (self.absOff(pins, self.y)) |_| self.ld(pins, &self.x, v), // LDX abs,Y
229
+
0xc0 => if (self.imm(pins)) |_| self.cmp(pins, self.y), // CPY #
230
+
0xc1 => if (self.zpXInd(pins)) |_| self.cmp(pins, self.a), // CMP (zp,X)
231
+
0xc4 => if (self.zp(pins)) |_| self.cmp(pins, self.y), // CPY zp
232
+
0xc5 => if (self.zp(pins)) |_| self.cmp(pins, self.a), // CMP zp
233
+
0xc6 => if (self.zp(pins)) |c| self.dec(pins, c), // DEC zp
234
+
0xc8 => if (self.imm(pins)) |_| self.inxy(pins, &self.y), // INY
235
+
0xc9 => if (self.imm(pins)) |_| self.cmp(pins, self.a), // CMP #
236
+
0xca => if (self.imm(pins)) |_| self.dexy(pins, &self.x), // DEY
237
+
0xcc => if (self.abs(pins)) |_| self.cmp(pins, self.y), // CPY abs
238
+
0xcd => if (self.abs(pins)) |_| self.cmp(pins, self.a), // CMP abs
239
+
0xce => if (self.abs(pins)) |c| self.dec(pins, c), // DEC abs
241
+
0xd0 => if (self.imm(pins)) |_| self.branch(pins, !self.status.zero), // BNE
242
+
0xd1 => if (self.zpIndY(pins)) |_| self.cmp(pins, self.a), // CMP (zp),Y
243
+
0xd5 => if (self.zpOff(pins, self.x)) |_| self.cmp(pins, self.a), // CMP zp,X
244
+
0xd6 => if (self.zpOff(pins, self.x)) |c| self.dec(pins, c), // DEC zp,X
0xd8 => self.set(pins, .decimal, false), // CLD
231
-
0xea => if (self.imm(pins)) self.fetch(pins), // NOP
233
-
0xf0 => if (self.imm(pins)) self.branch(pins, self.status.zero), // BEQ
246
+
0xd9 => if (self.absOff(pins, self.y)) |_| self.cmp(pins, self.a), // CMP abs,Y
247
+
0xdd => if (self.absOff(pins, self.x)) |_| self.cmp(pins, self.a), // CMP abs,X
248
+
0xde => if (self.absOff(pins, self.x)) |c| self.dec(pins, c), // DEC abs,X
250
+
0xe0 => if (self.imm(pins)) |_| self.cmp(pins, self.x), // CPX #
251
+
0xe1 => if (self.zpXInd(pins)) |_| self.sbc(pins, v), // SBC (zp,X)
252
+
0xe4 => if (self.zp(pins)) |_| self.cmp(pins, self.x), // CPX zp
253
+
0xe5 => if (self.zp(pins)) |_| self.sbc(pins, v), // SBC zp
254
+
0xe6 => if (self.zp(pins)) |c| self.inc(pins, c), // INC zp
255
+
0xe8 => if (self.imm(pins)) |_| self.inxy(pins, &self.x), // INX
256
+
0xe9 => if (self.imm(pins)) |_| self.sbc(pins, v), // SBC #
257
+
0xea => if (self.imm(pins)) |_| self.fetch(pins), // NOP
258
+
0xec => if (self.abs(pins)) |_| self.cmp(pins, self.x), // CPX abs
259
+
0xed => if (self.abs(pins)) |_| self.sbc(pins, v), // SBC abs
260
+
0xee => if (self.abs(pins)) |c| self.inc(pins, c), // INC abs
262
+
0xf0 => if (self.imm(pins)) |_| self.branch(pins, self.status.zero), // BEQ
263
+
0xf1 => if (self.zpIndY(pins)) |_| self.sbc(pins, v), // SBC (zp),Y
264
+
0xf5 => if (self.zpOff(pins, self.x)) |_| self.sbc(pins, v), // SBC zp,X
265
+
0xf6 => if (self.zpOff(pins, self.x)) |c| self.inc(pins, c), // INC zp,X
0xf8 => self.set(pins, .decimal, true), // SED
267
+
0xf9 => if (self.absOff(pins, self.y)) |_| self.sbc(pins, v), // SBC abs,Y
268
+
0xfd => if (self.absOff(pins, self.x)) |_| self.sbc(pins, v), // SBC abs,X
269
+
0xfe => if (self.absOff(pins, self.x)) |c| self.inc(pins, c), // INC abs,X
236
-
else => log.err("UNHANDLED OP={X}", .{self.opcode}),
272
+
log.err("UNHANDLED OP={X}", .{self.opcode});
240
-
inline fn imm(self: *Cpu, pins: *zesty.Pins) bool {
278
+
inline fn imm(self: *Cpu, pins: *zesty.Pins) ?u3 {
246
-
else => return true,
284
+
else => return self.cycle - 1,
250
-
inline fn zp(self: *Cpu, pins: *zesty.Pins) bool {
288
+
inline fn zp(self: *Cpu, pins: *zesty.Pins) ?u3 {
···
self.hilo = .{ .lo = pins.cpu_data };
pins.cpu_addr = self.hilo.addr();
260
-
else => return true,
298
+
else => return self.cycle - 2,
264
-
inline fn zpOff(self: *Cpu, pins: *zesty.Pins, v: u8) bool {
302
+
inline fn zpOff(self: *Cpu, pins: *zesty.Pins, v: u8) ?u3 {
···
pins.cpu_addr = self.hilo.addr();
278
-
else => return true,
316
+
else => return self.cycle - 3,
282
-
inline fn abs(self: *Cpu, pins: *zesty.Pins) bool {
320
+
inline fn abs(self: *Cpu, pins: *zesty.Pins) ?u3 {
···
self.hilo.hi = pins.cpu_data;
pins.cpu_addr = self.hilo.addr();
297
-
else => return true,
335
+
else => return self.cycle - 3,
301
-
inline fn absOff(self: *Cpu, pins: *zesty.Pins, v: u8) bool {
339
+
inline fn absOff(self: *Cpu, pins: *zesty.Pins, v: u8) ?u3 {
···
pins.cpu_addr = self.hilo.addr();
320
-
else => return true,
358
+
else => return self.cycle - 4,
324
-
inline fn zpXInd(self: *Cpu, pins: *zesty.Pins) bool {
362
+
inline fn zpXInd(self: *Cpu, pins: *zesty.Pins) ?u3 {
···
self.hilo.hi = pins.cpu_data;
pins.cpu_addr = self.hilo.addr();
347
-
else => return true,
385
+
else => return self.cycle - 5,
351
-
inline fn zpIndY(self: *Cpu, pins: *zesty.Pins) bool {
389
+
inline fn zpIndY(self: *Cpu, pins: *zesty.Pins) ?u3 {
···
pins.cpu_addr = self.hilo.addr();
370
-
else => return true,
408
+
else => return self.cycle - 5,
inline fn fetch(self: *Cpu, pins: *zesty.Pins) void {
···
486
-
inline fn dec(self: *Cpu, pins: *zesty.Pins, v: *u8) void {
524
+
inline fn adc(self: *Cpu, pins: *zesty.Pins, v: u8) void {
525
+
var result, var carry = @addWithOverflow(self.a, @intFromBool(self.status.carry));
526
+
// TODO: implement optional support for decimal mode
527
+
result, carry = @addWithOverflow(result, v);
529
+
self.status.carry = carry > 0;
530
+
self.setNZ(result);
531
+
// Overflow bit is set if both inputs have the same sign,
532
+
// and the output has a different sign
533
+
self.status.overflow = ~(self.a ^ v) & (self.a ^ result) & 0x80 > 0;
537
+
inline fn sbc(self: *Cpu, pins: *zesty.Pins, v: u8) void {
538
+
self.adc(pins, ~v);
540
+
inline fn cmp(self: *Cpu, pins: *zesty.Pins, v: u8) void {
541
+
// a CMP is basically a SBC in disguise
542
+
const result, const carry = @addWithOverflow(v, ~pins.cpu_data +% 1);
543
+
self.status.carry = carry > 0;
544
+
self.setNZ(result);
547
+
inline fn inxy(self: *Cpu, pins: *zesty.Pins, v: *u8) void {
553
+
inline fn dexy(self: *Cpu, pins: *zesty.Pins, v: *u8) void {
558
+
inline fn inc(self: *Cpu, pins: *zesty.Pins, c: u3) void {
561
+
// Dummy write? (Not sure why the processor does this)
562
+
self.hilo = .{ .lo = pins.cpu_data };
563
+
pins.cpu_rw = .write;
566
+
self.hilo.lo +%= 1;
567
+
self.setNZ(self.hilo.lo);
568
+
pins.cpu_data = self.hilo.lo;
569
+
pins.cpu_rw = .write;
571
+
else => self.fetch(pins),
574
+
inline fn dec(self: *Cpu, pins: *zesty.Pins, c: u3) void {
577
+
// Dummy write? (Not sure why the processor does this)
578
+
self.hilo = .{ .lo = pins.cpu_data };
579
+
pins.cpu_rw = .write;
582
+
self.hilo.lo -%= 1;
583
+
self.setNZ(self.hilo.lo);
584
+
pins.cpu_data = self.hilo.lo;
585
+
pins.cpu_rw = .write;
587
+
else => self.fetch(pins),
590
+
inline fn bit(self: *Cpu, pins: *zesty.Pins) void {
591
+
const status: Status = .from(pins.cpu_data);
592
+
self.status.negative = status.negative;
593
+
self.status.overflow = status.overflow;
594
+
self.status.zero = (self.a & pins.cpu_data) == 0;
//------------------------------------------------------
···
514
-
pins.cpu_addr = self.pc;
620
+
pins.cpu_addr = pc;
if (!page_crossed) self.fetchAt(pins, pc);
else => self.fetchAt(pins, self.hilo.addr()),
···
inline fn offsetWithPageFaultBehavior(
806
+
comptime signed: bool,
702
-
self.lo, const page_crossed = if (!signed and v < 0x80)
703
-
@addWithOverflow(self.lo, v)
808
+
const is_negative = signed and v >= 0x80;
809
+
self.lo, const page_crossed = if (is_negative)
// v should NEVER be lower than 0x80, but saturate down to 0 to be safe
706
-
@subWithOverflow(self.lo, v -| 0x80);
811
+
@subWithOverflow(self.lo, v - 0x80)
813
+
@addWithOverflow(self.lo, v);
// If we haven't crossed the page boundary, skip over the next cycle.
709
-
defer self.hi +%= page_crossed;
818
+
self.hi -%= page_crossed
820
+
self.hi +%= page_crossed;
return .{ self.addr(), page_crossed > 0 };
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