commit 98b9dd0405f68b0b32ad278d5bc3b43a428890e8 · pci.express/frostium

+42 -26

components/ukernel/arch/amd64/boot.zig

···

       95
       95
        
           bootstrapAPs();

     

       96
       96
        
       

     

       97
       97
        
           // Calibrate our TSC

     

       98
       98
       -
           const rate = arch.tsc.get_tsc_rate();

     

       99
       99
       -
           log.info("TSC estimated CPU MHz = {?}", .{rate / 1000});

     

       98
       98
       +
           arch.tsc.calibrate_pit() catch {

     

       99
       99
       +
               log.info("Failed to calibrate with PIT!", .{});

     

       100
       100
       +
               arch.instructions.die();

     

       101
       101
       +
           };

     

       102
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       +
           log.info("TSC estimate: {} MHz", .{arch.tsc.tsc_khz / 1000});

     

       100
       103
        
       

     

       101
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           log.info("Setting up scheduling...", .{});

     

       102
       102
       -
           // // Initialize the APIC

     

       103
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       -
           // // Map the APIC first!

     

       104
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       -
           // const apic_base = common.mm.physToHHDM([*]volatile u8, 0xFEE0_0000);

     

       105
       105
       -
           // common.mm.paging.mapPhys(.{

     

       106
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       -
           //     .vaddr = @intFromPtr(apic_base),

     

       107
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       -
           //     .paddr = 0xFEE0_0000,

     

       108
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       -
           //     .size = 0x1000,

     

       109
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       -
           //     .memory_type = .DeviceUncacheable,

     

       110
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       -
           //     .perms = .{

     

       111
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       -
           //         .executable = false,

     

       112
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       -
           //         .userspace_accessible = false,

     

       113
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       -
           //         .writable = true,

     

       114
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       -
           //     },

     

       115
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       -
           // }) catch @panic("apic bruh");

     

       116
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       -
           // const apic: arch.interrupts.apic.LAPIC = .{ .xapic = apic_base };

     

       117
       117
       -
           // arch.interrupts.apic.init.initialSetup(apic);

     

       105
       105
       +
       

     

       106
       106
       +
           initApic() catch |err| {

     

       107
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       +
               log.err("Failed to set up APIC! {}", .{err});

     

       108
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       +
               @panic("apic");

     

       109
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       +
           };

     

       118
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       119
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           log.info("Allocating code for userspace...", .{});

     

       120
       112
        
       

     
···

       147
       139
        
           const IA32_STAR = arch.registers.MSR(u64, 0xC0000081);

     

       148
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           const star_value: u64 = 0 | @as(u64, arch.structures.gdt.StandardGdt.selectors.kernel_code) << 32 | (@as(u64, arch.structures.gdt.StandardGdt.selectors.tss_desc + 8) | 3) << 48;

     

       149
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           IA32_STAR.write(star_value);

     

       150
       150
       -
           log.debug("Wrote 0x{x:0>16} to IA32_STAR", .{star_value});

     

       151
       142
        
       

     

       152
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           // Set up the EFER MSR with SCE (System Call Enable)

     

       153
       144
        
           const IA32_EFER = arch.registers.MSR(u64, 0xC0000080);

     

       154
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           const efer_val = IA32_EFER.read() | 0b1;

     

       155
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           IA32_EFER.write(efer_val);

     

       156
       156
       -
           log.debug("Wrote 0x{x:0>16} to IA32_EFER", .{efer_val});

     

       157
       147
        
       

     

       158
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           // Set up LSTAR with the syscall handler and FMASK to clear interrupts

     

       159
       149
        
           const IA32_LSTAR = arch.registers.MSR(u64, 0xC0000082);

     

       160
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           IA32_LSTAR.write(@intFromPtr(syscall_entry));

     

       161
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       162
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       -
           log.debug("Wrote 0x{x:0>16} to IA32_LSTAR", .{@intFromPtr(syscall_entry)});

     

       163
       163
       -
       

     

       164
       152
        
           const IA32_FMASK = arch.registers.MSR(u64, 0xC0000084);

     

       165
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           IA32_FMASK.write(1 << 9);

     

       166
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       -
           log.debug("Wrote 0x{x:0>16} to IA32_FMASK", .{1 << 9});

     

       167
       154
        
       }

     

       168
       155
        
       

     

       169
       156
        
       const syscall_entry = @extern(*anyopaque, .{

     
···

       216
       203
        
           unreachable;

     

       217
       204
        
       }

     

       218
       205
        
       

     

       206
       206
       +
       fn initApic() !void {

     

       207
       207
       +
           const has_x2apic = limine_requests.mp.response.?.flags.x2apic;

     

       208
       208
       +
           arch.interrupts.apic.singleton = switch (has_x2apic) {

     

       209
       209
       +
               true => .x2apic,

     

       210
       210
       +
               false => blk: {

     

       211
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       +
                   // Map the APIC first!

     

       212
       212
       +
                   const apic_base = common.mm.physToHHDM([*]volatile u8, 0xFEE0_0000);

     

       213
       213
       +
                   try common.mm.paging.mapPhys(.{

     

       214
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       +
                       .vaddr = @intFromPtr(apic_base),

     

       215
       215
       +
                       .paddr = 0xFEE0_0000,

     

       216
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       +
                       .size = 0x1000,

     

       217
       217
       +
                       .memory_type = .DeviceUncacheable,

     

       218
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       +
                       .perms = .{

     

       219
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       +
                           .executable = false,

     

       220
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       +
                           .userspace_accessible = false,

     

       221
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       +
                           .writable = true,

     

       222
       222
       +
                       },

     

       223
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       +
                   });

     

       224
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       +
                   break :blk .{ .xapic = apic_base };

     

       225
       225
       +
               },

     

       226
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       +
           };

     

       227
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       +
           // Set up the spurious vector and the TPR

     

       228
       228
       +
           arch.interrupts.apic.init.initialSetup();

     

       229
       229
       +
       

     

       230
       230
       +
           // Calibrate the APIC timer

     

       231
       231
       +
           arch.interrupts.apic.init.calibrateTimer();

     

       232
       232
       +
       

     

       233
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       +
           // Enable periodic interrupts

     

       234
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       +
           arch.interrupts.apic.init.enablePeriodicInterrupt(1000);

     

       235
       235
       +
       }

     

       236
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       +
       

     

       219
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       fn initConsole() void {

     

       220
       238
        
           if (limine_requests.framebuffer.response) |fb_response| {

     

       221
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               if (fb_response.framebuffer_count > 0) {

     
···

       246
       264
        
           arch.per_cpu_init_data.idt.general_protection_fault.installHandler(gpf);

     

       247
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           arch.per_cpu_init_data.idt.page_fault.installHandler(page_fault);

     

       248
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           arch.per_cpu_init_data.idt.interrupts[0xFF - 32].installHandler(arch.interrupts.apic.spurious_interrupt_handler);

     

       249
       249
       -
       

     

       250
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       -
           // Install the PIT handler

     

       251
       251
       -
           arch.per_cpu_init_data.idt.interrupts[0].installHandler(arch.interrupts.pit.handler);

     

       267
       267
       +
           arch.per_cpu_init_data.idt.interrupts[48 - 32].installHandler(arch.interrupts.apic.periodic_handler);

     

       252
       268
        
       

     

       253
       269
        
           // Load the Idt Register

     

       254
       270
        
           const reg: Idt.Idtr = .{ .addr = idt_addr, .limit = @sizeOf(Idt) - 1 };

+145 -6

components/ukernel/arch/amd64/interrupts/apic.zig

···

       2
       2
        
       const arch = @import("../root.zig");

     

       3
       3
        
       const log = std.log.scoped(.apic);

     

       4
       4
        
       

     

       5
       5
       +
       pub var lapic_timer_khz: usize = 0;

     

       6
       6
       +
       

     

       7
       7
       +
       // tbh every cpu will be either x2apic or not, and if xapic it will

     

       8
       8
       +
       // have the exact same base address anyways so this is fine

     

       9
       9
       +
       pub var singleton: LAPIC = undefined;

     

       10
       10
       +
       

     

       5
       11
        
       // Must instantiate this!

     

       6
       12
        
       pub const LAPIC = union(enum) {

     

       7
       13
        
           xapic: [*]volatile u8,

     
···

       43
       49
        
               _reserved1: u19 = 0,

     

       44
       50
        
           };

     

       45
       51
        
       

     

       46
       46
       -
           pub fn getSpuriousInterruptRegister(lapic: Self) VersionRegister {

     

       52
       52
       +
           pub fn getSpuriousInterruptRegister(lapic: Self) SpuriousInterruptRegister {

     

       47
       53
        
               return @bitCast(lapic.getRegister(.spurious_vector));

     

       48
       54
        
           }

     

       49
       55
        
       

     
···

       51
       57
        
               lapic.setRegister(.spurious_vector, @bitCast(val));

     

       52
       58
        
           }

     

       53
       59
        
       

     

       60
       60
       +
           // Task Priority

     

       61
       61
       +
           pub const TaskPriorityRegister = packed struct(u32) {

     

       62
       62
       +
               priority_sub_class: u4,

     

       63
       63
       +
               priority_class: u4,

     

       64
       64
       +
               _reserved0: u24 = 0,

     

       65
       65
       +
           };

     

       66
       66
       +
       

     

       67
       67
       +
           pub fn getTaskPriorityRegister(lapic: Self) TaskPriorityRegister {

     

       68
       68
       +
               return @bitCast(lapic.getRegister(.task_priority));

     

       69
       69
       +
           }

     

       70
       70
       +
       

     

       71
       71
       +
           pub fn setTaskPriorityRegister(lapic: Self, val: TaskPriorityRegister) void {

     

       72
       72
       +
               lapic.setRegister(.task_priority, @bitCast(val));

     

       73
       73
       +
           }

     

       74
       74
       +
       

     

       75
       75
       +
           // Initial Count

     

       76
       76
       +
           pub fn setInitialCountRegister(lapic: Self, count: u32) void {

     

       77
       77
       +
               lapic.setRegister(.initial_count, count);

     

       78
       78
       +
           }

     

       79
       79
       +
       

     

       80
       80
       +
           // Current Count

     

       81
       81
       +
           pub fn getCurrentCountRegister(lapic: Self) u32 {

     

       82
       82
       +
               return lapic.getRegister(.current_count);

     

       83
       83
       +
           }

     

       84
       84
       +
       

     

       85
       85
       +
           // Divide Configuration

     

       86
       86
       +
           pub const DivideConfigurationRegister = enum(u32) {

     

       87
       87
       +
               div2 = 0,

     

       88
       88
       +
               div4 = 1,

     

       89
       89
       +
               div8 = 2,

     

       90
       90
       +
               div16 = 3,

     

       91
       91
       +
               div32 = 8,

     

       92
       92
       +
               div64 = 9,

     

       93
       93
       +
               div128 = 10,

     

       94
       94
       +
               div1 = 11,

     

       95
       95
       +
           };

     

       96
       96
       +
       

     

       97
       97
       +
           pub fn getDivideConfigurationRegister(lapic: LAPIC) DivideConfigurationRegister {

     

       98
       98
       +
               return @enumFromInt(lapic.getRegister(.divide_configuration));

     

       99
       99
       +
           }

     

       100
       100
       +
       

     

       101
       101
       +
           pub fn setDivideConfigurationRegister(lapic: LAPIC, register: DivideConfigurationRegister) void {

     

       102
       102
       +
               lapic.setRegister(.divide_configuration, @intFromEnum(register));

     

       103
       103
       +
           }

     

       104
       104
       +
       

     

       105
       105
       +
           // LVT Timer Register

     

       106
       106
       +
           pub const LVTTimerRegister = packed struct(u32) {

     

       107
       107
       +
               idt_entry: u8,

     

       108
       108
       +
               _reserved0: u4 = 0,

     

       109
       109
       +
               status: DeliveryStatus = .idle,

     

       110
       110
       +
               _reserved1: u3 = 0,

     

       111
       111
       +
               masked: bool,

     

       112
       112
       +
               mode: Mode,

     

       113
       113
       +
               _reserved2: u13 = 0,

     

       114
       114
       +
       

     

       115
       115
       +
               pub const DeliveryStatus = enum(u1) {

     

       116
       116
       +
                   idle = 0,

     

       117
       117
       +
                   send_pending = 1,

     

       118
       118
       +
               };

     

       119
       119
       +
       

     

       120
       120
       +
               pub const Mode = enum(u2) {

     

       121
       121
       +
                   oneshot = 0,

     

       122
       122
       +
                   periodic = 1,

     

       123
       123
       +
                   tsc_deadline = 2,

     

       124
       124
       +
               };

     

       125
       125
       +
           };

     

       126
       126
       +
       

     

       127
       127
       +
           pub fn getLVTTimerRegister(lapic: LAPIC) LVTTimerRegister {

     

       128
       128
       +
               return @enumFromInt(lapic.getRegister(.lvt_timer));

     

       129
       129
       +
           }

     

       130
       130
       +
       

     

       131
       131
       +
           pub fn setLVTTimerRegister(lapic: LAPIC, register: LVTTimerRegister) void {

     

       132
       132
       +
               lapic.setRegister(.lvt_timer, @bitCast(register));

     

       133
       133
       +
           }

     

       134
       134
       +
       

     

       54
       135
        
           pub fn getRegister(lapic: Self, reg: Register) u32 {

     

       55
       136
        
               switch (lapic) {

     

       56
       137
        
                   .xapic => |base| {

     
···

       144
       225
        
       

     

       145
       226
        
       pub const init = struct {

     

       146
       227
        
           // Get the APIC ready (call first)

     

       147
       147
       -
           pub fn initialSetup(lapic: LAPIC) void {

     

       148
       148
       -
               lapic.setSpuriousInterruptRegister(.{

     

       228
       228
       +
           pub fn initialSetup() void {

     

       229
       229
       +
               singleton.setSpuriousInterruptRegister(.{

     

       149
       230
        
                   .apic_soft_enable = true,

     

       150
       231
        
                   .idt_entry = 0xFF,

     

       151
       232
        
               });

     

       152
       152
       -
               var lol = arch.instructions.cpuid.cpuid(0x15, 0x00);

     

       153
       153
       -
               lol = arch.instructions.cpuid.cpuid(0x40000010, 0x00);

     

       233
       233
       +
               // lapic.setTaskPriorityRegister(.{

     

       234
       234
       +
               //     .priority_class = 0,

     

       235
       235
       +
               //     .priority_sub_class = 0,

     

       236
       236
       +
               // });

     

       154
       237
        
           }

     

       155
       238
        
       

     

       156
       156
       -
           // Calibrate the APIC timer

     

       239
       239
       +
           pub fn calibrateTimer() void {

     

       240
       240
       +
               singleton.setDivideConfigurationRegister(.div2);

     

       241
       241
       +
               singleton.setLVTTimerRegister(.{

     

       242
       242
       +
                   .idt_entry = 0x69,

     

       243
       243
       +
                   .mode = .oneshot,

     

       244
       244
       +
                   .masked = true,

     

       245
       245
       +
               });

     

       157
       246
        
       

     

       247
       247
       +
               var warmup_clk_count: u64 = 0;

     

       248
       248
       +
               for (0..5) |_| {

     

       249
       249
       +
                   singleton.setInitialCountRegister(0xFFFF_FFFF);

     

       250
       250
       +
                   arch.tsc.delay_poll(1);

     

       251
       251
       +
                   const count = singleton.getCurrentCountRegister();

     

       252
       252
       +
                   singleton.setInitialCountRegister(0);

     

       253
       253
       +
       

     

       254
       254
       +
                   warmup_clk_count += 0xFFFF_FFFF - count;

     

       255
       255
       +
               }

     

       256
       256
       +
       

     

       257
       257
       +
               std.mem.doNotOptimizeAway(&warmup_clk_count);

     

       258
       258
       +
       

     

       259
       259
       +
               // Now, do it again

     

       260
       260
       +
               var tick_count: u64 = 0;

     

       261
       261
       +
               for (0..5) |_| {

     

       262
       262
       +
                   singleton.setInitialCountRegister(0xFFFF_FFFF);

     

       263
       263
       +
                   arch.tsc.delay_poll(5);

     

       264
       264
       +
                   const count = singleton.getCurrentCountRegister();

     

       265
       265
       +
                   singleton.setInitialCountRegister(0);

     

       266
       266
       +
       

     

       267
       267
       +
                   tick_count += 0xFFFF_FFFF - count;

     

       268
       268
       +
               }

     

       269
       269
       +
       

     

       270
       270
       +
               // This would be the number of ticks per 5ms interval

     

       271
       271
       +
               const norm = tick_count / 5;

     

       272
       272
       +
       

     

       273
       273
       +
               lapic_timer_khz = norm / 5;

     

       274
       274
       +
       

     

       275
       275
       +
               log.debug("APIC timer: {} kHz", .{lapic_timer_khz});

     

       276
       276
       +
           }

     

       277
       277
       +
       

     

       278
       278
       +
           pub fn enablePeriodicInterrupt(ms: usize) void {

     

       279
       279
       +
               singleton.setInitialCountRegister(0);

     

       280
       280
       +
               singleton.setDivideConfigurationRegister(.div2);

     

       281
       281
       +
       

     

       282
       282
       +
               singleton.setLVTTimerRegister(.{

     

       283
       283
       +
                   .idt_entry = 48,

     

       284
       284
       +
                   .mode = .periodic,

     

       285
       285
       +
                   .masked = false,

     

       286
       286
       +
               });

     

       287
       287
       +
       

     

       288
       288
       +
               const ticks: u32 = @truncate(lapic_timer_khz * ms);

     

       289
       289
       +
       

     

       290
       290
       +
               singleton.setInitialCountRegister(ticks);

     

       291
       291
       +
           }

     

       158
       292
        
       };

     

       159
       293
        
       

     

       160
       294
        
       pub fn spurious_interrupt_handler(_: *arch.structures.Idt.InterruptStackFrame) callconv(.{ .x86_64_interrupt = .{} }) void {

     

       161
       295
        
           log.warn("Got a spurious interrupt!", .{});

     

       162
       296
        
       }

     

       297
       297
       +
       

     

       298
       298
       +
       pub fn periodic_handler(_: *arch.structures.Idt.InterruptStackFrame) callconv(.{ .x86_64_interrupt = .{} }) void {

     

       299
       299
       +
           log.warn("Got an ACPI timer interrupt!", .{});

     

       300
       300
       +
           singleton.setRegister(.eoi, 0);

     

       301
       301
       +
       }

+12 -3

components/ukernel/arch/amd64/tsc.zig

···

       2
       2
        
       const out = arch.port.out;

     

       3
       3
        
       const in = arch.port.in;

     

       4
       4
        
       

     

       5
       5
       +
       pub var tsc_khz: usize = 0;

     

       6
       6
       +
       

     

       5
       7
        
       pub inline fn rdtsc() u64 {

     

       6
       8
        
           var low: u32 = undefined;

     

       7
       9
        
           var high: u32 = undefined;

     
···

       17
       19
        
       /// This should be called if we cannot get the TSC rate from

     

       18
       20
        
       /// CPUID.15h and 16h on Intel platforms. The calibration will be done

     

       19
       21
        
       /// against the 8254 PIT.

     

       20
       20
       -
       pub fn get_tsc_rate() ?usize {

     

       22
       22
       +
       pub fn calibrate_pit() !void {

     

       21
       23
        
           // Set up the PIC

     

       22
       24
        
           arch.interrupts.pic.init();

     

       23
       25
        
       

     
···

       40
       42
        
               pollcnt += 1;

     

       41
       43
        
           }

     

       42
       44
        
       

     

       43
       43
       -
           if (pollcnt < 1000) return null;

     

       45
       45
       +
           if (pollcnt < 1000) return error.PitError;

     

       46
       46
       +
       

     

       47
       47
       +
           tsc_khz = (end - start) / 50;

     

       48
       48
       +
       }

     

       44
       49
        
       

     

       45
       45
       -
           return (end - start) / 50;

     

       50
       50
       +
       /// Delay for a set amount of ms using crappy polling

     

       51
       51
       +
       pub fn delay_poll(ms: usize) void {

     

       52
       52
       +
           const start = rdtsc();

     

       53
       53
       +
           const target = start + ms * tsc_khz;

     

       54
       54
       +
           while (rdtsc() < target) {}

     

       46
       55
        
       }

-2

components/ukernel/common/loader.zig

···

       20
       20
        
               const vaddr_shift = entry.p_vaddr - real_vaddr;

     

       21
       21
        
               const memsz_pages = std.mem.alignForward(usize, vaddr_shift + entry.p_memsz, std.heap.pageSize());

     

       22
       22
        
       

     

       23
       23
       -
               log.debug("Allocating 0x{x} bytes (0x{x} real) to 0x{x:0>16} from offset 0x{x}", .{ entry.p_filesz, memsz_pages, entry.p_vaddr, entry.p_offset });

     

       24
       24
       -
       

     

       25
       23
        
               const page_backing = try common.init_data.bootmem.allocPhys(memsz_pages);

     

       26
       24
        
               try paging.mapPhys(.{

     

       27
       25
        
                   .vaddr = real_vaddr,