commit bee02dcebc2231b1cb60ed09248b6d076e8b628d · pci.express/frostium

components/root_server/src/main.zig

···

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       export fn _start() callconv(.c) noreturn {

     

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           // _ = os.syscall1(SYS_poke, 0xB16B00B5BADBABE);

     

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           // _ = os.syscall1(SYS_exit, 0x69696969);

     

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           asm volatile ("int3");

     

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           asm volatile (

     

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               \\ mov $0x69696969, %%rdi

     

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               \\ xor %%rsi, %%rsi

+5 -86

components/ukernel/arch/amd64/boot.zig

···

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           // Add in a framebuffer if found

     

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           initConsole();

     

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           // Get basic information through CPUID

     

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           arch.instructions.cpuid.init();

     

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           // Add in ACPI/dtb if found, prefer ACPI

     

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           initHwDesc();

     
···

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           init_syscalls();

     

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       +
           arch.interrupts.apic.armTimer(1000);

     

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           enter_userspace(entry, 0x69, 0x7ffe_0001_0000);

     

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       }

     

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           // Calibrate the APIC timer

     

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           arch.interrupts.apic.init.calibrateTimer();

     

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           // Enable periodic interrupts

     

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           arch.interrupts.apic.init.enablePeriodicInterrupt(1000);

     

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           // Enable one-shot interrupts

     

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           arch.interrupts.apic.init.enableOneshotInterrupt();

     

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       }

     

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       fn initConsole() void {

     
···

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                       .blue_mask_size = fb.blue_mask_size,

     

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                       .blue_mask_shift = fb.blue_mask_shift,

     

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                   });

     

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                   // common.init_data.console = flanterm.init(

     

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                   //     //malloc and free

     

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                   //     null,

     

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                   //     null,

     

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                   //     // fb info

     

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                   //     fb.address,

     

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                   //     fb.width,

     

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                   //     fb.height,

     

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                   //     fb.pitch,

     

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                   //     fb.red_mask_size,

     

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                   //     fb.red_mask_shift,

     

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                   //     fb.green_mask_size,

     

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                   //     fb.green_mask_shift,

     

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                   //     fb.blue_mask_size,

     

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                   //     fb.blue_mask_shift,

     

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                   //     // canvas

     

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                   //     null,

     

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                   //     // colors

     

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                   //     flanterm.ansi_colors,

     

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                   //     flanterm.bold_ansi_colors,

     

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                   //     // default bg and fg

     

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                   //     null,

     

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                   //     null,

     

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                   //     // default bright bg and fg

     

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                   //     null,

     

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                   //     null,

     

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                   //     // font

     

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                   //     null,

     

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                   //     // font width and height

     

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                   //     0,

     

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                   //     0,

     

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                   //     // font spacing

     

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                   //     1,

     

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                   //     // font scale x and y

     

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                   //     font_scale_x,

     

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                   //     font_scale_y,

     

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                   //     // margin

     

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                   //     0,

     

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                   // );

     

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               }

     

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           }

     

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       }

     
···

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               common.init_data.hardware_description = .{ .acpi_rsdp = rsdp_response.address };

     

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           }

     

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       }

     

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       -
       

     

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       // TODO: update the type reflection thing to make a custom

     

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       // function type for the ISR

     

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       pub const PageFaultErrorCode = packed struct(u64) {

     

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           present: bool,

     

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           write: bool,

     

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           user: bool,

     

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           reserved_write: bool,

     

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           instruction_fetch: bool,

     

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           protection_key: bool,

     

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           shadow_stack: bool,

     

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           _reserved: u8,

     

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           sgx: bool,

     

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           _reserved2: u48,

     

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           pub fn val(self: *const PageFaultErrorCode) u64 {

     

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               return @bitCast(self.*);

     

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           }

     

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       };

     

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       // pub fn page_fault(stack_frame: *arch.structures.Idt.InterruptStackFrame, err_code_u64: u64) callconv(.{ .x86_64_interrupt = .{} }) void {

     

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       //     const err_code: PageFaultErrorCode = @bitCast(err_code_u64);

     

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       //     log.err("PAGE FAULT @ 0x{x:0>16}, code 0x{x}!!!!!!!!!!!", .{ stack_frame.instruction_pointer, err_code.val() });

     

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       //     const cr2 = arch.registers.ControlRegisters.Cr2.read();

     

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       //     switch (err_code.write) {

     

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       //         true => log.err("Tried to write to vaddr 0x{x:0>16}", .{cr2}),

     

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       //         false => log.err("Tried to read from vaddr 0x{x:0>16}", .{cr2}),

     

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       //     }

     

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       //     log.err("dying...", .{});

     

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       //     arch.instructions.die();

     

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       // }

     

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       // pub fn breakpoint_handler(stack_frame: *Idt.InterruptStackFrame) callconv(.{ .x86_64_interrupt = .{} }) void {

     

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       //     log.warn("Breakpoint @ 0x{x:0>16}, returning execution...", .{stack_frame.instruction_pointer});

     

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       // }

     

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       // pub fn gpf(stack_frame: *Idt.InterruptStackFrame, err_code: u64) callconv(.{ .x86_64_interrupt = .{} }) void {

     

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       //     log.warn("gpf @ 0x{x:0>16} ERR CODE {}, returning execution...", .{ stack_frame.instruction_pointer, err_code });

     

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       //     arch.instructions.die();

     

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       // }

     

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       // pub fn double_fault(stack_frame: *Idt.InterruptStackFrame, err_code: u64) callconv(.{ .x86_64_interrupt = .{} }) noreturn {

     

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       //     log.err("FATAL DOUBLE FAULT @ 0x{x:0>16}, code 0x{x}!!!!!!!!!!!", .{ stack_frame.instruction_pointer, err_code });

     

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       //     log.err("dying...", .{});

     

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       //     arch.instructions.die();

     

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       // }

     

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       fn bootstrapAPs() void {

     

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           log.info("Bootstrapping APs...", .{});

+31

components/ukernel/arch/amd64/instructions/cpuid.zig

···

       1
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       +
       // Do all the needed CPUID calls here, and store the info for later use

     

       2
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       +
       const std = @import("std");

     

       3
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       const arch = @import("../root.zig");

     

       4
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       +
       

     

       5
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       +
       pub const captured = struct {

     

       6
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       +
           pub var vendor_str: [12]u8 = undefined;

     

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       +
       };

     

       8
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       +
       pub fn init() void {

     

       9
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       +
           capture_vendor_str();

     

       10
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           capture_cpu_features();

     

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       +
       }

     

       12
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       +
       

     

       13
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       fn capture_vendor_str() void {

     

       14
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           const res = cpuid(0, 0);

     

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       +
           @memcpy(captured.vendor_str[0..4], std.mem.asBytes(&res.ebx));

     

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           @memcpy(captured.vendor_str[4..8], std.mem.asBytes(&res.edx));

     

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       +
           @memcpy(captured.vendor_str[8..12], std.mem.asBytes(&res.ecx));

     

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       +
       }

     

       19
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       +
       

     

       20
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       fn capture_cpu_features() void {

     

       21
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       +
           const res = cpuid(1, 0);

     

       22
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       +
           const feat_ecx: FeaturesEcx = @bitCast(res.ecx);

     

       23
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           arch.interrupts.apic.tsc_deadline_available = feat_ecx.tsc_deadline;

     

       24
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       +
       }

     

       25
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       +
       

     

       26
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       +
       const FeaturesEcx = packed struct(u32) {

     

       27
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       +
           _reserved0: u23,

     

       28
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           tsc_deadline: bool,

     

       29
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       +
           _reserved1: u8,

     

       30
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       +
       };

     

       31
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       +
       

     

       1
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       pub inline fn cpuid(leaf: u32, sub: u32) DefaultResults {

     

       2
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           var eax: u32 = undefined;

     

       3
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           var ebx: u32 = undefined;

+25 -7

components/ukernel/arch/amd64/interrupts/apic.zig

···

       3
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       const log = std.log.scoped(.apic);

     

       4
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       5
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       pub var lapic_timer_khz: usize = 0;

     

       6
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       +
       pub var tsc_deadline_available = false;

     

       6
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       7
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       // tbh every cpu will be either x2apic or not, and if xapic it will

     

       8
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       // have the exact same base address anyways so this is fine

     
···

       277
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               log.debug("APIC timer: {} kHz", .{lapic_timer_khz});

     

       278
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           }

     

       279
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       280
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       -
           pub fn enablePeriodicInterrupt(ms: usize) void {

     

       281
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       -
               singleton.setInitialCountRegister(0);

     

       282
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       -
               singleton.setDivideConfigurationRegister(.div2);

     

       281
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       +
           pub fn enableOneshotInterrupt() void {

     

       282
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       +
               const mode: LAPIC.LVTTimerRegister.Mode = switch (tsc_deadline_available) {

     

       283
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       +
                   true => .tsc_deadline,

     

       284
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       +
                   false => blk: {

     

       285
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       +
                       singleton.setInitialCountRegister(0);

     

       286
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       +
                       singleton.setDivideConfigurationRegister(.div2);

     

       287
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       +
                       break :blk .oneshot;

     

       288
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       +
                   },

     

       289
       289
       +
               };

     

       283
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       291
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       +
               // TODO: detect and support tsc_deadline, ditto @ armTimer

     

       284
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               singleton.setLVTTimerRegister(.{

     

       285
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                   .idt_entry = 48,

     

       286
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       -
                   .mode = .periodic,

     

       294
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       +
                   .mode = mode,

     

       287
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                   .masked = false,

     

       288
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               });

     

       297
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       +
           }

     

       298
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       +
       };

     

       289
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       300
       300
       +
       pub fn armTimer(ms: usize) void {

     

       301
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       +
           if (tsc_deadline_available) {

     

       302
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       +
               const IA32_TSC_DEADLINE = arch.registers.MSR(u64, 0x6E0);

     

       303
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       +
               const delta = arch.tsc.tsc_khz * ms;

     

       304
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       +
               const target = arch.tsc.rdtsc() + delta;

     

       305
       305
       +
       

     

       306
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       +
               IA32_TSC_DEADLINE.write(target);

     

       307
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       +
           } else {

     

       290
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               const ticks: u32 = @truncate(lapic_timer_khz * ms);

     

       291
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       -
       

     

       292
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               singleton.setInitialCountRegister(ticks);

     

       293
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           }

     

       294
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       -
       };

     

       311
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       +
       }

     

       295
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       296
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       pub fn spurious_interrupt_handler(_: *arch.interrupts.idt.InterruptFrame(u64)) callconv(.{ .x86_64_sysv = .{} }) void {

     

       297
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           log.warn("Got a spurious interrupt!", .{});

     

       298
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       }

     

       299
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       300
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       pub fn periodic_handler(stack_trace: *arch.interrupts.idt.InterruptFrame(u64)) callconv(.{ .x86_64_sysv = .{} }) void {

     

       301
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       -
           log.warn("Got an APIC timer interrupt, incrementing user's %rsi...", .{});

     

       318
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       +
           log.warn("Got an APIC timer interrupt, incrementing user's rsi...", .{});

     

       302
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           stack_trace.regs.rsi += 1;

     

       303
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           singleton.setRegister(.eoi, 0);

     

       321
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       +
           armTimer(1000);

     

       304
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       }