···
# gcc.arch to its features (as in /proc/cpuinfo)
7
+
# Spec: https://gitlab.com/x86-psABIs/x86-64-ABI/
10
+
x86-64-v2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
11
+
x86-64-v3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "fma" ];
12
+
x86-64-v4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "avx512" "fma" ];
14
+
nehalem = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
westmere = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
sandybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
ivybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
···
# a superior CPU has all the features of an inferior and is able to build and test code for it
54
+
x86-64-v2 = [ "x86-64" ];
55
+
x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
56
+
x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
48
-
sandybridge = [ "westmere" ] ++ inferiors.westmere;
49
-
ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
50
-
haswell = [ "ivybridge" ] ++ inferiors.ivybridge;
51
-
broadwell = [ "haswell" ] ++ inferiors.haswell;
52
-
skylake = [ "broadwell" ] ++ inferiors.broadwell;
53
-
skylake-avx512 = [ "skylake" ] ++ inferiors.skylake;
60
+
nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
61
+
westmere = [ "nehalem" ] ++ inferiors.nehalem;
62
+
sandybridge = [ "westmere" ] ++ inferiors.westmere;
63
+
ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
65
+
haswell = lib.unique ([ "ivybridge" "x86-64-v3" ] ++ inferiors.ivybridge ++ inferiors.x86-64-v3);
66
+
broadwell = [ "haswell" ] ++ inferiors.haswell;
67
+
skylake = [ "broadwell" ] ++ inferiors.broadwell;
69
+
skylake-avx512 = lib.unique ([ "skylake" "x86-64-v4" ] ++ inferiors.skylake ++ inferiors.x86-64-v4);
cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
57
-
cascadelake = [ "skylake-avx512" ] ++ inferiors.cannonlake;
73
+
cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
···
# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
# https://en.wikichip.org/wiki/amd/microarchitectures/zen
# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
90
-
znver1 = [ "skylake" ] ++ inferiors.skylake;
107
+
znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
znver2 = [ "znver1" ] ++ inferiors.znver1;
znver3 = [ "znver2" ] ++ inferiors.znver2;
93
-
znver4 = [ "znver3" ] ++ inferiors.znver3;
110
+
znver4 = lib.unique ([ "znver3" "x86-64-v4" ] ++ inferiors.znver3 ++ inferiors.x86-64-v4);