-28
pkgs/applications/science/electronics/hal-hardware-analyzer/4.4.1-newer-spdlog-fmt-compat.patch
-28
pkgs/applications/science/electronics/hal-hardware-analyzer/4.4.1-newer-spdlog-fmt-compat.patch
···-diff --git a/plugins/module_identification/src/api/module_identification.cpp b/plugins/module_identification/src/api/module_identification.cpp-const u32 num_threads = std::min(config.m_max_thread_count, std::thread::hardware_concurrency() - 1);-- log_info("module_identification", "running with {} threads and {} multithreading priority", num_threads, config.m_multithreading_priority);-+ log_info("module_identification", "running with {} threads and {} multithreading priority", num_threads, fmt::underlying(config.m_multithreading_priority));
+12
-29
pkgs/applications/science/electronics/hal-hardware-analyzer/default.nix
pkgs/by-name/ha/hal-hardware-analyzer/package.nix
+12
-29
pkgs/applications/science/electronics/hal-hardware-analyzer/default.nix
pkgs/by-name/ha/hal-hardware-analyzer/package.nix
···············description = "Comprehensive reverse engineering and manipulation framework for gate-level netlists";
-13
pkgs/applications/science/electronics/hal-hardware-analyzer/resynthesis-fix-narrowing-conversion.patch
-13
pkgs/applications/science/electronics/hal-hardware-analyzer/resynthesis-fix-narrowing-conversion.patch
···-Result<u32> resynthesize_subgraph_of_type(Netlist* nl, const std::vector<const GateType*>& gate_types, GateLibrary* target_gl)
+9
pkgs/by-name/ve/verilator/package.nix
+9
pkgs/by-name/ve/verilator/package.nix
······+url = "https://github.com/verilator/verilator/commit/2aa260a03b67d3fe86bc64b8a59183f8dc21e117.patch";
-4
pkgs/top-level/all-packages.nix
-4
pkgs/top-level/all-packages.nix
···