commit 495d11bf33dda14b599c60c01c6a64d974346682 · pci.express/frostium

+162

components/ukernel/arch/amd64/apic.zig

···

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       const std = @import("std");

     

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       const arch = @import("root.zig");

     

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       const log = std.log.scoped(.apic);

     

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       // Must instantiate this!

     

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       pub const LAPIC = union(enum) {

     

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           xapic: [*]volatile u8,

     

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           x2apic,

     

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           const Self = @This();

     

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           // ID Register

     

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           pub const IdRegister = packed struct(u32) {

     

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               _reserved0: u24 = 0,

     

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               id: u8,

     

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           };

     

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           pub fn getIdRegister(lapic: Self) IdRegister {

     

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               return @bitCast(lapic.getRegister(.lapic_id));

     

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           }

     

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           // Version Register

     

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           pub const VersionRegister = packed struct(u32) {

     

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               version: u8,

     

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               _reserved0: u8 = 0,

     

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               max_lvt_entry: u8,

     

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               support_for_eoi_broadcast_suppression: bool,

     

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               _reserved1: u7 = 0,

     

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           };

     

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           pub fn getVersionRegister(lapic: Self) VersionRegister {

     

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               return @bitCast(lapic.getRegister(.version));

     

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           }

     

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           // Spurious Interrupt

     

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           pub const SpuriousInterruptRegister = packed struct(u32) {

     

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               idt_entry: u8,

     

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               apic_soft_enable: bool,

     

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               focus_processor_checking: bool = false,

     

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               _reserved0: u2 = 0,

     

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               eoi_broadcast_suppression: bool = false,

     

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               _reserved1: u19 = 0,

     

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           };

     

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           pub fn getSpuriousInterruptRegister(lapic: Self) VersionRegister {

     

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               return @bitCast(lapic.getRegister(.spurious_vector));

     

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           }

     

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           pub fn setSpuriousInterruptRegister(lapic: Self, val: SpuriousInterruptRegister) void {

     

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               lapic.setRegister(.spurious_vector, @bitCast(val));

     

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           }

     

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           pub fn getRegister(lapic: Self, reg: Register) u32 {

     

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               switch (lapic) {

     

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                   .xapic => |base| {

     

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                       const ptr: *align(0x10) volatile u32 = @ptrCast(@alignCast(base + reg.xapic()));

     

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                       return ptr.*;

     

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                   },

     

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                   .x2apic => {

     

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                       return arch.registers.readMSR(u32, reg.x2apic());

     

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                   },

     

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               }

     

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           }

     

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           pub fn setRegister(lapic: Self, reg: Register, value: u32) void {

     

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               switch (lapic) {

     

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                   .xapic => |base| {

     

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                       const ptr: *align(0x10) volatile u32 = @ptrCast(@alignCast(base + reg.xapic()));

     

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                       ptr.* = value;

     

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                   },

     

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                   .x2apic => {

     

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                       arch.registers.writeMSR(u32, reg.x2apic(), value);

     

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                   },

     

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               }

     

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           }

     

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           pub const Register = enum(u32) {

     

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               // From Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3

     

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               lapic_id = 0x2,

     

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               version = 0x3,

     

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               task_priority = 0x8,

     

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               process_priority = 0xa,

     

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               eoi = 0xb,

     

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               logical_destination = 0xd,

     

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               spurious_vector = 0xf,

     

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               in_service_0_31 = 0x10,

     

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               in_service_63_32 = 0x11,

     

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               in_service_95_64 = 0x12,

     

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               in_service_127_96 = 0x13,

     

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               in_service_159_128 = 0x14,

     

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               in_service_191_160 = 0x15,

     

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               in_service_223_192 = 0x16,

     

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               in_service_255_224 = 0x17,

     

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               trigger_mode_0_31 = 0x18,

     

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               trigger_mode_63_32 = 0x19,

     

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               trigger_mode_95_64 = 0x1a,

     

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               trigger_mode_127_96 = 0x1b,

     

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               trigger_mode_159_128 = 0x1c,

     

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               trigger_mode_191_160 = 0x1d,

     

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               trigger_mode_223_192 = 0x1e,

     

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               trigger_mode_255_224 = 0x1f,

     

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               interrupt_request_0_31 = 0x20,

     

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               interrupt_request_63_32 = 0x21,

     

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               interrupt_request_95_64 = 0x22,

     

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               interrupt_request_127_96 = 0x23,

     

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               interrupt_request_159_128 = 0x24,

     

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               interrupt_request_191_160 = 0x25,

     

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               interrupt_request_223_192 = 0x26,

     

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               interrupt_request_255_224 = 0x27,

     

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               error_status = 0x28,

     

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               lvt_cmi = 0x2f,

     

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               interrupt_command_0_31 = 0x30,

     

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               interrupt_command_32_63 = 0x31,

     

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               lvt_timer = 0x32,

     

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               lvt_thermal_sensor = 0x33,

     

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               lvt_performance_monitoring = 0x34,

     

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               lvt_lint0 = 0x35,

     

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               lvt_lint1 = 0x36,

     

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               lvt_error = 0x37,

     

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               initial_count = 0x38,

     

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               current_count = 0x39,

     

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               divide_configuration = 0x3e,

     

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               self_ipi = 0x3f,

     

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               const Self = @This();

     

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               // Get an offset to apply to the xAPIC base

     

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               pub fn xapic(reg: Register) usize {

     

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                   return @intFromEnum(reg) * 0x10;

     

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               }

     

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               // Get an MSR number to write to

     

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               pub fn x2apic(reg: Register) u32 {

     

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                   return 0x800 | @intFromEnum(reg);

     

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               }

     

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           };

     

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       };

     

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       pub const init = struct {

     

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           // Get the APIC ready (call first)

     

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           pub fn initialSetup(lapic: LAPIC) void {

     

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               lapic.setSpuriousInterruptRegister(.{

     

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                   .apic_soft_enable = true,

     

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                   .idt_entry = 0xFF,

     

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               });

     

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               var lol = arch.instructions.cpuid.cpuid(0x15, 0x00);

     

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               lol = arch.instructions.cpuid.cpuid(0x40000010, 0x00);

     

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           }

     

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           // Calibrate the APIC timer

     

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       };

     

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       pub fn spurious_interrupt_handler(_: *arch.structures.Idt.InterruptStackFrame) callconv(.{ .x86_64_interrupt = .{} }) void {

     

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           log.warn("Got a spurious interrupt!", .{});

     

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       }

+31 -47

components/ukernel/arch/amd64/boot.zig

···

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       const StandardGdt = arch.structures.gdt.StandardGdt;

     

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       const Tss = arch.structures.tss.Tss;

     

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       var per_cpu_init_data: PerCpuInitData = .{};

     

       12
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       -
       

     

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       pub const limine_requests = struct {

     

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           export var start_marker: limine.RequestsStartMarker linksection(".limine_reqs_start") = .{};

     

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           export var end_marker: limine.RequestsEndMarker linksection(".limine_reqs_end") = .{};

     
···

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           }

     

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           // Initialize per-cpu data (GDT and TSS)

     

       76
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       -
           per_cpu_init_data.init();

     

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           arch.per_cpu_init_data.init(limine_requests.mp.response.?.cpu_count);

     

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           // Install the IDT

     

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           initIdt();

     
···

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           bootstrapAPs();

     

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           // Set up our own GDT and TSS

     

       85
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           const gdt = &per_cpu_init_data.gdt_buf[0];

     

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           const gdt = &arch.per_cpu_init_data.gdt_buf[0];

     

       86
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           gdt.* = .{};

     

       87
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           const tss = &per_cpu_init_data.tss_buf[0];

     

       85
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           const tss = &arch.per_cpu_init_data.tss_buf[0];

     

       88
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           // TSS rsp 0x3800

     

       89
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           tss.* = .{

     

       90
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               .rsp0 = 0x3800,

     
···

       95
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           gdt.tss_desc.set_tss_addr(tss);

     

       96
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           gdt.load();

     

       97
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           log.info("BSP successfully setup GDT+TSS!", .{});

     

       96
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       97
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           log.info("Setting up scheduling...", .{});

     

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           // Initialize the APIC

     

       99
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           // Map the APIC first!

     

       100
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           const apic_base = common.mm.physToHHDM([*]volatile u8, 0xFEE0_0000);

     

       101
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           common.mm.paging.mapPhys(.{

     

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               .vaddr = @intFromPtr(apic_base),

     

       103
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               .paddr = 0xFEE0_0000,

     

       104
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               .size = 0x1000,

     

       105
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               .memory_type = .DeviceUncacheable,

     

       106
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               .perms = .{

     

       107
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                   .executable = false,

     

       108
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                   .userspace_accessible = false,

     

       109
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                   .writable = true,

     

       110
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               },

     

       111
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           }) catch @panic("apic bruh");

     

       112
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           const apic: arch.apic.LAPIC = .{ .xapic = apic_base };

     

       113
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           arch.apic.init.initialSetup(apic);

     

       98
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       99
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           log.info("Allocating code for userspace...", .{});

     

       100
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···

       219
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       }

     

       220
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       221
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       pub fn initIdt() void {

     

       222
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       -
           const idt_addr: usize = @intFromPtr(per_cpu_init_data.idt);

     

       238
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       +
           const idt_addr: usize = @intFromPtr(arch.per_cpu_init_data.idt);

     

       223
       239
        
       

     

       224
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           // Install the known exception handlers

     

       225
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       -
           per_cpu_init_data.idt.breakpoint.installHandler(breakpoint_handler);

     

       226
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           per_cpu_init_data.idt.double_fault.installHandler(double_fault);

     

       227
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           per_cpu_init_data.idt.general_protection_fault.installHandler(gpf);

     

       228
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           per_cpu_init_data.idt.page_fault.installHandler(page_fault);

     

       241
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           arch.per_cpu_init_data.idt.breakpoint.installHandler(breakpoint_handler);

     

       242
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           arch.per_cpu_init_data.idt.double_fault.installHandler(double_fault);

     

       243
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       +
           arch.per_cpu_init_data.idt.general_protection_fault.installHandler(gpf);

     

       244
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       +
           arch.per_cpu_init_data.idt.page_fault.installHandler(page_fault);

     

       245
       245
       +
           arch.per_cpu_init_data.idt.interrupts[0xFF - 32].installHandler(arch.apic.spurious_interrupt_handler);

     

       229
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       230
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           // Load the Idt Register

     

       231
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           const reg: Idt.Idtr = .{ .addr = idt_addr, .limit = @sizeOf(Idt) - 1 };

     
···

       234
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       235
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       // TODO: update the type reflection thing to make a custom

     

       236
       253
        
       // function type for the ISR

     

       237
       237
       -
       pub const PageFaultErrorCode = packed struct {

     

       254
       254
       +
       pub const PageFaultErrorCode = packed struct(u64) {

     

       238
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           present: bool,

     

       239
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           write: bool,

     

       240
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           user: bool,

     
···

       288
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       289
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       fn ap_init(mp_info: *limine.SmpMpFeature.MpInfo) callconv(.c) noreturn {

     

       290
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           // Set up the IDT

     

       291
       291
       -
           const idt_addr: usize = @intFromPtr(per_cpu_init_data.idt);

     

       308
       308
       +
           const idt_addr: usize = @intFromPtr(arch.per_cpu_init_data.idt);

     

       292
       309
        
           const reg: Idt.Idtr = .{ .addr = idt_addr, .limit = @sizeOf(Idt) - 1 };

     

       293
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           reg.load();

     

       294
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       295
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           // Set up our GDT and TSS

     

       296
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       -
           const gdt = &per_cpu_init_data.gdt_buf[mp_info.processor_id];

     

       313
       313
       +
           const gdt = &arch.per_cpu_init_data.gdt_buf[mp_info.processor_id];

     

       297
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           gdt.* = .{};

     

       298
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       -
           const tss = &per_cpu_init_data.tss_buf[mp_info.processor_id];

     

       315
       315
       +
           const tss = &arch.per_cpu_init_data.tss_buf[mp_info.processor_id];

     

       299
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           tss.* = .{};

     

       300
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       301
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           gdt.tss_desc.set_tss_addr(tss);

     
···

       305
       322
        
       

     

       306
       323
        
           arch.instructions.die();

     

       307
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       }

     

       308
       308
       -
       

     

       309
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       -
       const PerCpuInitData = struct {

     

       310
       310
       -
           gdt_buf: []StandardGdt = undefined,

     

       311
       311
       -
           tss_buf: []Tss = undefined,

     

       312
       312
       -
           idt: *Idt = undefined,

     

       313
       313
       -
       

     

       314
       314
       -
           const Self = @This();

     

       315
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       -
           pub fn init(self: *Self) void {

     

       316
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       -
               // 1. Allocate an IDT

     

       317
       317
       -
               const idt_addr = common.init_data.bootmem.allocMem(@sizeOf(Idt)) catch |err| {

     

       318
       318
       -
                   std.log.err("init PerCpuInitData: IDT alloc failed: {}", .{err});

     

       319
       319
       -
                   @panic("rip bozo");

     

       320
       320
       -
               };

     

       321
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       -
               self.idt = @ptrFromInt(idt_addr);

     

       322
       322
       -
       

     

       323
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       -
               // 2. Allocate space for GDT and TSS data

     

       324
       324
       -
               const cpu_count = limine_requests.mp.response.?.cpu_count;

     

       325
       325
       -
               const gdt_size = @sizeOf(StandardGdt);

     

       326
       326
       -
               const tss_size = @sizeOf(Tss);

     

       327
       327
       -
       

     

       328
       328
       -
               const total_required_size = gdt_size * cpu_count + tss_size * cpu_count;

     

       329
       329
       -
               const buf: [*]u8 = @ptrFromInt(common.init_data.bootmem.allocMem(total_required_size) catch |err| {

     

       330
       330
       -
                   std.log.err("init PerCpuInitData: GDT/TSS alloc failed: {}", .{err});

     

       331
       331
       -
                   @panic("rip bozo");

     

       332
       332
       -
               });

     

       333
       333
       -
       

     

       334
       334
       -
               // 3. Transmute and fill out the structure

     

       335
       335
       -
               const gdt_buf: [*]StandardGdt = @ptrCast(@alignCast(buf[0 .. gdt_size * cpu_count]));

     

       336
       336
       -
               const tss_buf: [*]Tss = @ptrCast(@alignCast(buf[gdt_size * cpu_count ..][0 .. tss_size * cpu_count]));

     

       337
       337
       -
               self.gdt_buf = gdt_buf[0..cpu_count];

     

       338
       338
       -
               self.tss_buf = tss_buf[0..cpu_count];

     

       339
       339
       -
           }

     

       340
       340
       -
       };

-5

components/ukernel/arch/amd64/instructions.zig

···

       1
       1
       -
       pub inline fn die() noreturn {

     

       2
       2
       -
           while (true) {

     

       3
       3
       -
               asm volatile ("hlt");

     

       4
       4
       -
           }

     

       5
       5
       -
       }

+30

components/ukernel/arch/amd64/instructions/cpuid.zig

···

       1
       1
       +
       pub inline fn cpuid(leaf: u32, sub: u32) DefaultResults {

     

       2
       2
       +
           var eax: u32 = undefined;

     

       3
       3
       +
           var ebx: u32 = undefined;

     

       4
       4
       +
           var edx: u32 = undefined;

     

       5
       5
       +
           var ecx: u32 = undefined;

     

       6
       6
       +
       

     

       7
       7
       +
           asm volatile (

     

       8
       8
       +
               \\cpuid

     

       9
       9
       +
               : [eax] "={eax}" (eax),

     

       10
       10
       +
                 [ebx] "={ebx}" (ebx),

     

       11
       11
       +
                 [edx] "={edx}" (edx),

     

       12
       12
       +
                 [ecx] "={ecx}" (ecx),

     

       13
       13
       +
               : [leaf] "{eax}" (leaf),

     

       14
       14
       +
                 [sub] "{ecx}" (sub),

     

       15
       15
       +
           );

     

       16
       16
       +
       

     

       17
       17
       +
           return .{

     

       18
       18
       +
               .eax = eax,

     

       19
       19
       +
               .ebx = ebx,

     

       20
       20
       +
               .ecx = ecx,

     

       21
       21
       +
               .edx = edx,

     

       22
       22
       +
           };

     

       23
       23
       +
       }

     

       24
       24
       +
       

     

       25
       25
       +
       pub const DefaultResults = struct {

     

       26
       26
       +
           eax: u32 = 0,

     

       27
       27
       +
           ebx: u32 = 0,

     

       28
       28
       +
           edx: u32 = 0,

     

       29
       29
       +
           ecx: u32 = 0,

     

       30
       30
       +
       };

+19

components/ukernel/arch/amd64/instructions/root.zig

···

       1
       1
       +
       pub const cpuid = @import("cpuid.zig");

     

       2
       2
       +
       

     

       3
       3
       +
       pub inline fn die() noreturn {

     

       4
       4
       +
           while (true) {

     

       5
       5
       +
               asm volatile ("hlt");

     

       6
       6
       +
           }

     

       7
       7
       +
       }

     

       8
       8
       +
       

     

       9
       9
       +
       pub inline fn rdtsc() u64 {

     

       10
       10
       +
           var low: u32 = undefined;

     

       11
       11
       +
           var high: u32 = undefined;

     

       12
       12
       +
       

     

       13
       13
       +
           asm volatile ("rdtsc"

     

       14
       14
       +
               : [low] "={eax}" (low),

     

       15
       15
       +
                 [high] "={eax}" (high),

     

       16
       16
       +
           );

     

       17
       17
       +
       

     

       18
       18
       +
           return (@as(u64, high) << 32) | @as(u64, low);

     

       19
       19
       +
       }

+1 -1

components/ukernel/arch/amd64/mm/paging.zig

···

       15
       15
        
       pub const PageTable = extern struct {

     

       16
       16
        
           entries: [512]Entry,

     

       17
       17
        
       

     

       18
       18
       -
           pub const Entry = packed struct {

     

       18
       18
       +
           pub const Entry = packed struct(u64) {

     

       19
       19
        
               present: bool,

     

       20
       20
        
               writable: bool,

     

       21
       21
        
               user_accessible: bool,

+46 -38

components/ukernel/arch/amd64/registers.zig

···

       32
       32
        
           };

     

       33
       33
        
       }

     

       34
       34
        
       

     

       35
       35
       +
       pub inline fn readMSR(comptime T: type, num: u32) T {

     

       36
       36
       +
           return switch (@bitSizeOf(T)) {

     

       37
       37
       +
               32 => @bitCast(asm volatile ("rdmsr"

     

       38
       38
       +
                   : [_] "={eax}" (-> u32),

     

       39
       39
       +
                   : [_] "{ecx}" (num),

     

       40
       40
       +
               )),

     

       41
       41
       +
               64 => blk: {

     

       42
       42
       +
                   var low_val: u32 = undefined;

     

       43
       43
       +
                   var high_val: u32 = undefined;

     

       44
       44
       +
                   asm volatile ("rdmsr"

     

       45
       45
       +
                       : [_] "={eax}" (low_val),

     

       46
       46
       +
                         [_] "={edx}" (high_val),

     

       47
       47
       +
                       : [_] "{ecx}" (num),

     

       48
       48
       +
                   );

     

       49
       49
       +
                   const combined_val = (@as(u64, high_val) << 32) | @as(u64, low_val);

     

       50
       50
       +
                   break :blk @as(T, combined_val);

     

       51
       51
       +
               },

     

       52
       52
       +
               else => @compileError("Unimplemented for type of this size"),

     

       53
       53
       +
           };

     

       54
       54
       +
       }

     

       55
       55
       +
       

     

       56
       56
       +
       pub inline fn writeMSR(comptime T: type, num: u32, val: T) void {

     

       57
       57
       +
           switch (@bitSizeOf(T)) {

     

       58
       58
       +
               32 => asm volatile ("wrmsr"

     

       59
       59
       +
                   :

     

       60
       60
       +
                   : [_] "{eax}" (val),

     

       61
       61
       +
                     [_] "{edx}" (@as(u32, 0)),

     

       62
       62
       +
                     [_] "{ecx}" (num),

     

       63
       63
       +
               ),

     

       64
       64
       +
               64 => {

     

       65
       65
       +
                   const low_val: u32 = @truncate(@as(u64, val));

     

       66
       66
       +
                   const high_val: u32 = @truncate(@as(u64, val >> 32));

     

       67
       67
       +
                   asm volatile ("wrmsr"

     

       68
       68
       +
                       :

     

       69
       69
       +
                       : [_] "{eax}" (low_val),

     

       70
       70
       +
                         [_] "{edx}" (high_val),

     

       71
       71
       +
                         [_] "{ecx}" (num),

     

       72
       72
       +
                   );

     

       73
       73
       +
               },

     

       74
       74
       +
               else => @compileError("Unimplemented for type of this size"),

     

       75
       75
       +
           }

     

       76
       76
       +
       }

     

       77
       77
       +
       

     

       35
       78
        
       pub fn MSR(comptime T: type, comptime num: u32) type {

     

       36
       79
        
           return struct {

     

       37
       80
        
               pub fn read() T {

     

       38
       38
       -
                   // TODO: switch on bit size to allow custom structs

     

       39
       39
       -
                   switch (T) {

     

       40
       40
       -
                       u32 => return asm volatile ("rdmsr"

     

       41
       41
       -
                           : [_] "={eax}" (-> u32),

     

       42
       42
       -
                           : [_] "{ecx}" (num),

     

       43
       43
       -
                       ),

     

       44
       44
       -
                       u64 => {

     

       45
       45
       -
                           var low_val: u32 = undefined;

     

       46
       46
       -
                           var high_val: u32 = undefined;

     

       47
       47
       -
                           asm volatile ("rdmsr"

     

       48
       48
       -
                               : [_] "={eax}" (low_val),

     

       49
       49
       -
                                 [_] "={edx}" (high_val),

     

       50
       50
       -
                               : [_] "{ecx}" (num),

     

       51
       51
       -
                           );

     

       52
       52
       -
                           return (@as(u64, high_val) << 32) | @as(u64, low_val);

     

       53
       53
       -
                       },

     

       54
       54
       -
                       else => @compileError("Unimplemented for type"),

     

       55
       55
       -
                   }

     

       81
       81
       +
                   return readMSR(T, num);

     

       56
       82
        
               }

     

       57
       57
       -
               pub fn write(value: T) void {

     

       58
       58
       -
                   switch (T) {

     

       59
       59
       -
                       u32 => asm volatile ("wrmsr"

     

       60
       60
       -
                           :

     

       61
       61
       -
                           : [_] "{eax}" (value),

     

       62
       62
       -
                             [_] "{edx}" (@as(u32, 0)),

     

       63
       63
       -
                             [_] "{ecx}" (num),

     

       64
       64
       -
                       ),

     

       65
       65
       -
                       u64 => {

     

       66
       66
       -
                           const low_val: u32 = @truncate(value);

     

       67
       67
       -
                           const high_val: u32 = @truncate(value >> 32);

     

       68
       68
       -
                           asm volatile ("wrmsr"

     

       69
       69
       -
                               :

     

       70
       70
       -
                               : [_] "{eax}" (low_val),

     

       71
       71
       -
                                 [_] "{edx}" (high_val),

     

       72
       72
       -
                                 [_] "{ecx}" (num),

     

       73
       73
       -
                           );

     

       74
       74
       -
                       },

     

       75
       75
       -
                       else => @compileError("Unimplemented for type"),

     

       76
       76
       -
                   }

     

       83
       83
       +
               pub fn write(val: T) void {

     

       84
       84
       +
                   writeMSR(T, num, val);

     

       77
       85
        
               }

     

       78
       86
        
           };

     

       79
       87
        
       }

+41 -1

components/ukernel/arch/amd64/root.zig

···

       1
       1
       +
       pub const apic = @import("apic.zig");

     

       1
       2
        
       pub const boot = @import("boot.zig");

     

       2
       2
       -
       pub const instructions = @import("instructions.zig");

     

       3
       3
       +
       pub const instructions = @import("instructions/root.zig");

     

       3
       4
        
       pub const mm = @import("mm/root.zig");

     

       5
       5
       +
       pub const port = @import("port.zig");

     

       4
       6
        
       pub const structures = @import("structures/root.zig");

     

       5
       7
        
       pub const registers = @import("registers.zig");

     

       6
       8
        
       const common = @import("common");

     
···

       17
       19
        
           .queryPageSize = pageSize,

     

       18
       20
        
       };

     

       19
       21
        
       pub const panic = std.debug.FullPanic(common.aux.panic);

     

       22
       22
       +
       

     

       23
       23
       +
       pub var per_cpu_init_data: PerCpuInitData = .{};

     

       24
       24
       +
       

     

       25
       25
       +
       const PerCpuInitData = struct {

     

       26
       26
       +
           const StandardGdt = structures.gdt.StandardGdt;

     

       27
       27
       +
           const Tss = structures.tss.Tss;

     

       28
       28
       +
           const Idt = structures.Idt;

     

       29
       29
       +
       

     

       30
       30
       +
           gdt_buf: []StandardGdt = undefined,

     

       31
       31
       +
           tss_buf: []Tss = undefined,

     

       32
       32
       +
           idt: *Idt = undefined,

     

       33
       33
       +
       

     

       34
       34
       +
           const Self = @This();

     

       35
       35
       +
           pub fn init(self: *Self, cpu_count: u64) void {

     

       36
       36
       +
               // 1. Allocate an IDT

     

       37
       37
       +
               const idt_addr = common.init_data.bootmem.allocMem(@sizeOf(Idt)) catch |err| {

     

       38
       38
       +
                   std.log.err("init PerCpuInitData: IDT alloc failed: {}", .{err});

     

       39
       39
       +
                   @panic("rip bozo");

     

       40
       40
       +
               };

     

       41
       41
       +
               self.idt = @ptrFromInt(idt_addr);

     

       42
       42
       +
       

     

       43
       43
       +
               // 2. Allocate space for GDT and TSS data

     

       44
       44
       +
               const gdt_size = @sizeOf(StandardGdt);

     

       45
       45
       +
               const tss_size = @sizeOf(Tss);

     

       46
       46
       +
       

     

       47
       47
       +
               const total_required_size = gdt_size * cpu_count + tss_size * cpu_count;

     

       48
       48
       +
               const buf: [*]u8 = @ptrFromInt(common.init_data.bootmem.allocMem(total_required_size) catch |err| {

     

       49
       49
       +
                   std.log.err("init PerCpuInitData: GDT/TSS alloc failed: {}", .{err});

     

       50
       50
       +
                   @panic("rip bozo");

     

       51
       51
       +
               });

     

       52
       52
       +
       

     

       53
       53
       +
               // 3. Transmute and fill out the structure

     

       54
       54
       +
               const gdt_buf: [*]StandardGdt = @ptrCast(@alignCast(buf[0 .. gdt_size * cpu_count]));

     

       55
       55
       +
               const tss_buf: [*]Tss = @ptrCast(@alignCast(buf[gdt_size * cpu_count ..][0 .. tss_size * cpu_count]));

     

       56
       56
       +
               self.gdt_buf = gdt_buf[0..cpu_count];

     

       57
       57
       +
               self.tss_buf = tss_buf[0..cpu_count];

     

       58
       58
       +
           }

     

       59
       59
       +
       };

     

       20
       60
        
       

     

       21
       61
        
       comptime {

     

       22
       62
        
           // Entry point (_start)

+2 -2

components/ukernel/arch/amd64/structures/Idt.zig

···

       105
       105
        
       

     

       106
       106
        
               const FuncType = @Type(FunctionTypeInfo);

     

       107
       107
        
       

     

       108
       108
       -
               pub const Options = packed struct {

     

       108
       108
       +
               pub const Options = packed struct(u16) {

     

       109
       109
        
                   /// Interrupt Stack Table Index

     

       110
       110
        
                   ist_index: u3,

     

       111
       111
        
                   _reserved: u5 = 0,

     
···

       144
       144
        
       }

     

       145
       145
        
       

     

       146
       146
        
       /// IDT Register

     

       147
       147
       -
       pub const Idtr = packed struct {

     

       147
       147
       +
       pub const Idtr = packed struct(u80) {

     

       148
       148
        
           limit: u16,

     

       149
       149
        
           addr: u64,

     

       150
       150

+5 -5

components/ukernel/arch/amd64/structures/gdt.zig

···

       2
       2
        
       const std = @import("std");

     

       3
       3
        
       const arch = @import("../root.zig");

     

       4
       4
        
       

     

       5
       5
       -
       pub const Descriptor = packed struct {

     

       5
       5
       +
       pub const Descriptor = packed struct(u64) {

     

       6
       6
        
           limit_low: u16 = 0,

     

       7
       7
        
           base_low: u16 = 0,

     

       8
       8
        
           base_mid: u8 = 0,

     
···

       13
       13
        
       

     

       14
       14
        
           const Self = @This();

     

       15
       15
        
       

     

       16
       16
       -
           pub const Access = packed struct {

     

       16
       16
       +
           pub const Access = packed struct(u8) {

     

       17
       17
        
               // Accessed

     

       18
       18
        
               accessed: bool = true,

     

       19
       19
        
               // Readable/Writable

     
···

       35
       35
        
               };

     

       36
       36
        
           };

     

       37
       37
        
       

     

       38
       38
       -
           pub const Flags = packed struct {

     

       38
       38
       +
           pub const Flags = packed struct(u4) {

     

       39
       39
        
               // Reserved

     

       40
       40
        
               _reserved: u1 = 0,

     

       41
       41
        
               // Long Mode code flag

     
···

       121
       121
        
           }

     

       122
       122
        
       };

     

       123
       123
        
       

     

       124
       124
       -
       pub const Gdtr = packed struct {

     

       124
       124
       +
       pub const Gdtr = packed struct(u80) {

     

       125
       125
        
           limit: u16,

     

       126
       126
        
           base: u64,

     

       127
       127
        
       

     
···

       134
       134
        
       };

     

       135
       135
        
       

     

       136
       136
        
       const TssDescriptor = extern struct {

     

       137
       137
       -
           const Low = packed struct {

     

       137
       137
       +
           const Low = packed struct(u64) {

     

       138
       138
        
               limit_low: u16 = 0,

     

       139
       139
        
               base_low: u16 = 0,

     

       140
       140
        
               base_mid: u8 = 0,